LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
use ieee.numeric_std.all;
USE STD.TEXTIO.ALL;

entity bin2onehot_tb is
end bin2onehot_tb;

architecture testbench_arch of bin2onehot_tb is
constant Tpd: time:= 6 ns;
signal addr_internal : std_logic_vector(5 downto 0) := "000000";
signal clk_internal, we_internal, oe_internal : std_logic;
signal data_internal : std_logic_vector(15 downto 0);
signal reducedDataInternal : std_logic_vector(3 downto 0);
signal dlugoscArgumentu : integer := 8;
signal nazwapliku : string(1 to dlugoscArgumentu);
file infile: text;       -- plik wymuszen
file outfile: text open WRITE_MODE is "wyniki.txt";   -- plik wynikow

--komponent ram20 ---------
component ram20d
    port (clk : in std_logic;
           we  : in std_logic;
           oe  : in std_logic;
           addr: in std_logic_vector(5 downto 0);
           data: inout std_logic_vector(15 downto 0));
end component;


--zamiana STD Logic Vector na Stringa
 function doStringa (SLV : std_logic_vector) return string is
    variable L : LINE;
  begin
    hwrite(L,SLV);
    return L.all;
  end function doStringa;

--procedura odczytu-----
procedure odczyt(signal datain : in std_logic_vector(15 downto 0);signal adres : out std_logic_vector(5 downto 0);
signal zegar : out std_logic;signal we : out std_logic;signal oe : out std_logic;
signal dataout : out std_logic_vector(3 downto 0)) is
variable readData : std_logic_vector(3 downto 0) := std_logic_vector(resize(ieee.numeric_std.signed(datain),dataout'length));
begin
	we <= '0';
	oe <= '1';
	wait for 1ns;
	zegar <= '1';
	wait for 1.1ns;
	zegar <= '0';
	--dataout <= readData;
	--wait for 1ns;
end procedure;

--procedura zapisu------
procedure zapis(signal danain : in std_logic_vector(3 downto 0); signal adres : out std_logic_vector(5 downto 0);
signal zegar : out std_logic;signal we : out std_logic;signal oe : out std_logic;
signal danaout : out std_logic_vector(15 downto 0)) is
--variable add : std_logic_vector(5 downto 0);
variable datka : std_logic_vector(15 downto 0) := std_logic_vector(resize(ieee.numeric_std.signed(danain), danaout'length));
begin
	danaout <= datka;
	we <= '1';
	oe <= '0';
	zegar <= '0';
	wait for 1ns;
	zegar <= '1';
	wait for 1ns;
	zegar <= '0';
	--wait for 1ns;

end procedure;

-- procedury lokalne
procedure slv2_to_file(slv1, slv2: in std_logic_vector; file f: text; header: boolean:=false) is
    variable text_out : line;
 begin
    if header then
	report "Rozpoczynam dzialanie z plikiem: " & nazwapliku severity note;
        write(text_out,string'("bin") & HT & string'("onehot"));
    else
        hwrite(text_out,slv1); write(text_out,HT); write(text_out,slv2);
    end if;
    writeline(f,text_out);

--wait for Tpd/2;
if (slv1 /= "U") and (slv1 /= "X") and (slv1 /= "") then
report "Zamiana liczby: " & doStringa(slv1) & " na: " & doStringa(slv2) severity note;
end if;
end procedure;

procedure slv1_from_file(signal slv1: out std_logic_vector; file f: text; nbit: positive:=4) is
    variable text_in : line;
    variable in_data : integer := 0;
 begin
    readline(f, text_in);  -- czytaj linie pliku wejsciowego
    read(text_in, in_data); -- pobierz zmienna in_data
    slv1 <= conv_std_logic_vector(in_data,nbit);
end procedure;

-- deklaracja komponentu badanego ------------------------------
    component bin2onehot
        port (
            bin : in  std_logic_vector (3 downto 0);
            onehot : out  std_logic_vector (9 downto 0)
        );
    end component;

    signal bin_internal : std_logic_vector (3 downto 0);
    signal onehot_internal : std_logic_vector (9 downto 0);

-- architektura testbench'a-------------------------------------
begin
    ramik : ram20d
    port map(clk => clk_internal,
	     we => we_internal,
	     oe => oe_internal,
	     addr => addr_internal,
	     data => data_internal);

    UUT : bin2onehot        -- unit under test
    port map ( bin => reducedDataInternal,
               onehot => onehot_internal);

    process -- process bez listy wrazliwosci
variable fstatus: file_open_status;

    begin
	file_open(fstatus,infile,nazwapliku,read_mode);
        slv2_to_file(bin_internal, onehot_internal, outfile, True); -- header
        czytaj: while not Endfile(infile) loop
	    --data_Internal <= (others => 'Z');
            slv1_from_file(bin_internal, infile); -- nowy wektor z pliku
	    zapis(bin_internal, addr_internal,clk_internal,we_internal,oe_internal,data_internal);
	    reducedDataInternal <= std_logic_vector(resize(ieee.numeric_std.signed(data_Internal), reducedDataInternal'length));
            wait for Tpd;
	    --odczyt(data_internal, addr_internal,clk_internal,we_internal,oe_internal,reducedDataInternal);
            slv2_to_file(reducedDataInternal, onehot_internal, outfile); -- kolejny wynik do pliku
	    addr_internal <= std_logic_vector(ieee.numeric_std.signed(addr_internal) + 1 );
        end loop czytaj;
        wait; -- zawies proces
    end process;
end testbench_arch;