library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Beep is
    Port ( E : in  STD_LOGIC;
           Clk : in  STD_LOGIC;
           Start : out  STD_LOGIC;
           Addr : out  STD_LOGIC_VECTOR (3 downto 0);
           Cmd : out  STD_LOGIC_VECTOR (3 downto 0);
           DATA : out  STD_LOGIC_VECTOR (11 downto 0));
end Beep;

architecture Behavioral of Beep is
   signal temp : UNSIGNED (4 downto 0):="00000";
   signal licznik : UNSIGNED (10 downto 0):="00000000000";
   signal st : STD_LOGIC:='0';
begin
   Addr<="1111"; --wszystkie kanaly
   Cmd<="0011";  --komenda update
   process (Clk, E)
   begin
   if rising_edge(Clk) and E='1' then
      if licznik = X"000" then st<='1';
         else st<='0';
      end if;
      licznik <= licznik + 1;
      if licznik = X"61B" then
         temp <= temp + 1;
         licznik<="00000000000";
      end if;
     end if;
   end process;

DATA<=STD_LOGIC_VECTOR(temp) & "0000000";
Start<=st;

end Behavioral;