`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/07/2019 03:46:23 PM
// Design Name:
// Module Name: fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module fsm(input clk, rst, start, output sin);
    localparam idle = 2'b01, A=1'b01, B=2'b10, C=2'b11;
    reg[1:0] stan, next;

    always @(posedge clk, posedge rst)
    if(rst)
        stan <=idle;

    else
        stan <=next;

    always @* begin
    next=idle;
        case(stan)
            idle: next = start?A:idle;
            A: next = B;
            B: next = C;
            C: next = idle;
            endcase
            end
        assign sin = (stan!=idle);

endmodule