tariq786

ethernet_test_top reset generation

Jul 27th, 2014
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  1. // `default_nettype none //commented by Tariq
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer: Joel Williams
  5. //
  6. // Create Date: 11:23:07 02/18/2011
  7. // Design Name:
  8. // Module Name: ethernet_test_top
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Simple test framework for the Atlys' 88E1111 chip
  15. //
  16. // Dependencies:
  17. //
  18. // Revision:
  19. // Revision 0.01 - File Created
  20. // Additional Comments:
  21. //
  22. //////////////////////////////////////////////////////////////////////////////////
  23. module ethernet_test_top(
  24. input wire clk_100_pin,
  25.  
  26. output wire PhyResetOut_pin,
  27. input wire MII_TX_CLK_pin, // 25 MHz clock for 100 Mbps - not used here
  28. output reg [7:0] GMII_TXD_pin,
  29. output reg GMII_TX_EN_pin,
  30. output reg GMII_TX_ER_pin,
  31. output wire GMII_TX_CLK_pin,
  32. input wire [7:0] GMII_RXD_pin,
  33. input wire GMII_RX_DV_pin,
  34. input wire GMII_RX_ER_pin,
  35. input wire GMII_RX_CLK_pin,
  36. output wire MDC_pin,
  37. inout wire MDIO_pin,
  38.  
  39. output wire [7:0] leds,
  40. // input wire [7:0] sw,
  41. input wire [5:0] btn,
  42.  
  43. output wire rs232_tx
  44. );
  45.  
  46. // System clock
  47. wire clk_100;
  48.  
  49. IBUFG ibufg_100 (
  50. .I(clk_100_pin),
  51. .O(clk_100));
  52.  
  53. // 125 MHz for PHY. 90 degree shifted clock drives PHY's GMII_TX_CLK.
  54. wire clk_125, clk_125_GTX_CLK, clk_125_GTX_CLK_n, pll_locked;
  55. wire pll_rst;
  56.  
  57. clk_125_tx clk_125_tx(
  58. .CLK_IN1(clk_100),
  59. .CLK_OUT1(clk_125), // 0 deg
  60. .CLK_OUT2(clk_125_GTX_CLK), // 90 deg
  61. .CLK_OUT3(),
  62. .RESET(pll_rst),
  63. .LOCKED(pll_locked));
  64.  
  65. // PLL reset logic
  66. // Based on http://forums.xilinx.com/t5/Spartan-Family-FPGAs/RESET-SIGNALS/m-p/133182#M10198
  67. reg [25:0] pll_status_counter = 0;
  68. always @(posedge clk_100)
  69. if (pll_locked)
  70. pll_status_counter <= 0;
  71. else
  72. pll_status_counter <= pll_status_counter + 1'b1;
  73.  
  74. assign pll_rst = (pll_status_counter > (2**26 - 26'd20)); // Reset for 20 cycles
  75.  
  76. // The USRP2 has a 125 MHz oscillator connected to clk_to_mac. While the
  77. // 88E1111 generates a 125 MHz reference (125CLK), this isn't connected.
  78. // We generate this clock from the Atlys' 100 MHz oscillator using the DCM.
  79. wire clk_to_mac;
  80. assign clk_to_mac = clk_125;
  81.  
  82. // USRP2 runs the GEMAC's FIFOs at 100 MHz, though this is buffered through a DCM.
  83. wire dsp_clk;
  84. assign dsp_clk = clk_125;
  85.  
  86. // USRP2 runs its CPU and the Wishbone bus at 50 MHz system clock, possibly due to
  87. // speed limitations in the Spartan-3. Let's try running it at full speed.
  88. wire wb_clk;
  89. assign wb_clk = clk_125;
  90.  
  91.  
  92. // Hold the FSMs in reset until the PLL has locked
  93. wire dsp_rst;
  94. reg sw_reconfig;
  95.  
  96. reset reset (
  97. .clk(clk_100),
  98. .pll_lock(pll_locked),
  99. .rst_1(),
  100.  
  101. .clk_2(dsp_clk),
  102. .rst_2(dsp_rst),
  103.  
  104. .ext_reset(sw_reconfig));
  105.  
  106. // Drive the GTX_CLK output from a DDR register
  107. wire GMII_GTX_CLK_int;
  108.  
  109. ODDR2 ODDR_gmii (
  110. .Q(GMII_TX_CLK_pin), // Data output (connect directly to top-level port)
  111. .C0(clk_125_GTX_CLK), // 0 degree clock input
  112. .C1(~clk_125_GTX_CLK), // 180 degree clock input
  113. .CE(1'b1), // Clock enable input
  114. .D0(1'b0), // Posedge data input
  115. .D1(1'b1), // Negedge data input
  116. .R(1'b0), // Synchronous reset input
  117. .S(1'b0) // Synchronous preset input
  118. );
  119.  
  120. // Register MAC outputs
  121. wire GMII_TX_EN, GMII_TX_ER;
  122. wire [7:0] GMII_TXD;
  123.  
  124. always @(posedge GMII_GTX_CLK_int)
  125. begin
  126. GMII_TX_EN_pin <= GMII_TX_EN;
  127. GMII_TX_ER_pin <= GMII_TX_ER;
  128. GMII_TXD_pin <= GMII_TXD;
  129. end
  130.  
  131. // LEDs for debugging
  132. reg [7:0] ledreg;
  133. assign leds = ledreg;
  134.  
  135. wire gemac_ready;
  136. wire [3:0] gemac_debug;
  137.  
  138. always @(posedge dsp_clk) begin
  139. ledreg <= {4'd0, gemac_debug};
  140. end
  141.  
  142. // Sync a pushbutton to FSM clock to initiate packet
  143.  
  144. wire sw_send_packet;
  145. edge_detect edge_detect_s1 (.async_sig(btn[0]), .clk(dsp_clk), .rise(), .fall(sw_send_packet));
  146. // edge_detect edge_detect_s2 (.async_sig(btn[1]), .clk(dsp_clk), .rise(), .fall(sw_reconfig));
  147.  
  148. initial
  149. begin
  150. sw_reconfig = 1'b0;
  151. repeat(10000) @(posedge dsp_clk);
  152. sw_reconfig = 1'b1;
  153. repeat(1000) @(posedge dsp_clk);
  154. sw_reconfig = 1'b0;
  155. end
  156.  
  157.  
  158. // The top module of the USRP2 MAC core
  159. localparam dw = 32; // WB data bus width
  160. localparam aw = 8; // WB address bus width
  161. wire wb_rst;
  162. wire rd2_dst_rdy, wr2_dst_rdy;
  163. wire wr2_src_rdy, rd2_src_rdy;
  164. wire [3:0] wr2_flags;
  165. wire [3:0] rd2_flags;
  166. wire [31:0] rd2_data;
  167. wire [31:0] wr2_data;
  168. wire [dw-1:0] wb_dat_o;
  169. wire [dw-1:0] wb_dat_i;
  170. wire [aw-1:0] wb_adr;
  171. wire wb_ack;
  172. wire wb_stb, wb_cyc, wb_we;
  173. wire [79:0] debug_mac;
  174.  
  175. simple_gemac_wrapper #(
  176. .RXFIFOSIZE(9), .TXFIFOSIZE(6)
  177. )
  178. simple_gemac_wrapper (
  179.  
  180. .clk125(clk_to_mac),
  181. .reset(wb_rst),
  182.  
  183. // PHY pins
  184. .GMII_GTX_CLK(GMII_GTX_CLK_int), .GMII_TX_EN(GMII_TX_EN),
  185. .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
  186. .GMII_RX_CLK(GMII_RX_CLK_pin), .GMII_RX_DV(GMII_RX_DV_pin),
  187. .GMII_RX_ER(GMII_RX_ER_pin), .GMII_RXD(GMII_RXD_pin),
  188. .mdio(MDIO_pin), .mdc(MDC_pin),
  189.  
  190. // I/O buses
  191. .sys_clk(dsp_clk),
  192. .rx_f36_data({rd2_flags,rd2_data}), .rx_f36_src_rdy(rd2_src_rdy), .rx_f36_dst_rdy(rd2_dst_rdy),
  193. .tx_f36_data({wr2_flags,wr2_data}), .tx_f36_src_rdy(wr2_src_rdy), .tx_f36_dst_rdy(wr2_dst_rdy),
  194.  
  195. // Wishbone signals
  196. .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),
  197. .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_o), .wb_dat_o(wb_dat_i),
  198.  
  199. .debug(debug_mac));
  200.  
  201. // After the PLL has locked, configure the MAC and PHY using a state machine
  202.  
  203. gemac_configure gemac_configure (
  204. .clk(wb_clk),
  205.  
  206. // Wishbone signals
  207. .wb_rst(wb_rst),
  208. .wb_stb(wb_stb),
  209. .wb_cyc(wb_cyc),
  210. .wb_ack(wb_ack),
  211. .wb_we(wb_we),
  212. .wb_adr(wb_adr[7:0]),
  213. .wb_dat_i(wb_dat_i),
  214. .wb_dat_o(wb_dat_o),
  215.  
  216. .phy_reset(PhyResetOut_pin), // Connect to PHY's reset pin
  217. .reset(dsp_rst),
  218. .debug(gemac_debug),
  219. .ready(gemac_ready)); // Signal to rest of the system that negotiation is complete
  220.  
  221.  
  222. // Send out Ethernet packets
  223. packet_sender packet_sender (
  224. .clk(dsp_clk),
  225. .reset(~gemac_ready),
  226. .wr_flags_o(wr2_flags),
  227. .wr_data_o(wr2_data),
  228. .wr_dst_rdy_i(wr2_dst_rdy),
  229. .wr_src_rdy_o(wr2_src_rdy),
  230.  
  231. // .packet_size_i(sw[7:0]),
  232. .start(sw_send_packet)
  233.  
  234. );
  235.  
  236.  
  237. // Receive Ethernet packets
  238. wire [7:0] udp_data_out;
  239. wire udp_data_out_en;
  240.  
  241. packet_receiver packet_receiver (
  242. .clk(dsp_clk),
  243. .reset(~gemac_ready),
  244.  
  245. .rd_flags_i(rd2_flags),
  246. .rd_data_i(rd2_data),
  247.  
  248. .rd_src_rdy_i(rd2_src_rdy),
  249. .rd_dst_rdy_o(rd2_dst_rdy),
  250.  
  251. .data_out_en(udp_data_out_en),
  252. .data_out(udp_data_out)
  253.  
  254. );
  255.  
  256.  
  257.  
  258. // UART and a packet-sized FIFO
  259.  
  260. // Baud rate generator - 150e6 / 976 / 16 ~ 9600 bps
  261. reg [10:0] baud_count = 0;
  262. reg en_16_x_baud;
  263.  
  264. always @(posedge dsp_clk)
  265. if (baud_count == 814) begin
  266. baud_count <= 1'b0;
  267. en_16_x_baud <= 1'b1;
  268. end else begin
  269. baud_count <= baud_count + 1'b1;
  270. en_16_x_baud <= 1'b0;
  271. end
  272.  
  273.  
  274. reg [7:0] uart_byte;
  275. reg uart_wr_en;
  276.  
  277. always @(posedge dsp_clk) begin
  278. uart_byte <= udp_data_out;
  279. uart_wr_en <= udp_data_out_en;
  280. end
  281.  
  282. // No buffer here - will overrun with packets > 16 bytes without more flow control or a FIFO
  283. uart_tx6 transmit (
  284. .data_in(uart_byte),
  285. .buffer_write(uart_wr_en),
  286. .buffer_reset(1'b0),
  287. .en_16_x_baud(en_16_x_baud),
  288. .serial_out(rs232_tx),
  289. .buffer_data_present(),
  290. .buffer_full(),
  291. .buffer_half_full(),
  292. .clk(dsp_clk));
  293.  
  294. endmodule
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