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  1. --------------------------------------------------------------------------------
  2. -- Title        : Memória da CPU
  3. -- Project      : CPU Multi-ciclo
  4. --------------------------------------------------------------------------------
  5. -- File         : Memory.vhd
  6. -- Author       : Emannuel Gomes Macêdo <egm@cin.ufpe.br>
  7. --                Fernando Raposo Camara da Silva <frcs@cin.ufpe.br>
  8. --                Pedro Machado Manhães de Castro <pmmc@cin.ufpe.br>
  9. --                Rodrigo Alves Costa <rac2@cin.ufpe.br>
  10. -- Organization : Universidade Federal de Pernambuco
  11. -- Created      : 26/07/2002
  12. -- Last update  : 23/11/2002
  13. -- Plataform    : Flex10K
  14. -- Simulators   : Altera Max+plus II
  15. -- Synthesizers :
  16. -- Targets      :
  17. -- Dependency   :
  18. --------------------------------------------------------------------------------
  19. -- Description  : Entidade responsável pela leitura e escrita em memória.
  20. --------------------------------------------------------------------------------
  21. -- Copyright (c) notice
  22. --      Universidade Federal de Pernambuco (UFPE).
  23. --      CIn - Centro de Informatica.
  24. --      Developed by computer science undergraduate students.
  25. --      This code may be used for educational and non-educational purposes as
  26. --      long as its copyright notice remains unchanged.
  27. --------------------------------------------------------------------------------
  28. -- Revisions        : 1
  29. -- Revision Number  : 1.0
  30. -- Version          : 1.1
  31. -- Date             : 23/11/2002
  32. -- Modifier         : Marcus Vinicius Lima e Machado <mvlm@cin.ufpe.br>
  33. --                    Paulo Roberto Santana Oliveira Filho <prsof@cin.ufpe.br>
  34. --                    Viviane Cristina Oliveira Aureliano <vcoa@cin.ufpe.br>
  35. -- Description      :
  36. --------------------------------------------------------------------------------
  37.  
  38. package ram_constants is
  39.     constant DATA_WIDTH : INTEGER := 8;
  40.     constant ADDR_WIDTH : INTEGER := 8;
  41.     constant INIT_FILE  : STRING  := "../instructions.mif";
  42. end ram_constants;
  43.  
  44. --*************************************************************************
  45. library IEEE;
  46. use IEEE.std_logic_1164.all;
  47. USE ieee.std_logic_arith.all;
  48.  
  49. library lpm;
  50. use lpm.lpm_components.all;
  51.  
  52. library work;
  53. use work.ram_constants.all;
  54. --*************************************************************************
  55.  
  56. --Short name: mem
  57. ENTITY Memory IS
  58.     PORT(
  59.         Address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);    -- Endereço de memória a ser lido
  60.         Clock   : IN  STD_LOGIC;                        -- Clock do sistema
  61.         Wr      : IN  STD_LOGIC;                        -- Indica se a memória será lida (0) ou escrita (1)
  62.         Sizein  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);     -- Indica se
  63.         Datain  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);    -- Valor lido da memória quando Wr = 0
  64.         Dataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)     -- Valor a ser escrito quando Wr = 1
  65.    );
  66. END Memory;
  67.  
  68. -- Arquitetura que define o comportamento da memória
  69. -- Simulation
  70. ARCHITECTURE behavioral_arch OF Memory IS
  71.     signal add          : bit_vector(7 downto 0);
  72.     signal addS0        : STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
  73.     signal addS1        : STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
  74.     signal addS2        : STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
  75.     signal addS3        : STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
  76.     signal dataoutS     : STD_LOGIC_VECTOR (31 DOWNTO 0);
  77.     signal datainS      : STD_LOGIC_VECTOR (31 DOWNTO 0);
  78.     signal dataoutS0    : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  79.     signal dataoutS1    : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  80.     signal dataoutS2    : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  81.     signal dataoutS3    : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  82.     signal datainS0     : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  83.     signal datainS1     : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  84.     signal datainS2     : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  85.     signal datainS3     : STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
  86.     signal wrS          : STD_LOGIC;
  87.     signal clockS       : STD_LOGIC;
  88.     signal add0         : integer;
  89.     signal add2         : integer;
  90.     signal add1         : integer;
  91.     signal add3         : integer;
  92.     signal addu         : unsigned(7 downto 0);
  93. BEGIN
  94.  
  95. ---- Usa apenas 8 bits menos significativos do endereço
  96.     add <= To_BitVector(Address(7 downto 0));
  97.  
  98. -- Conversão de bit-vector em inteiro
  99.     addu(0) <= To_StdULogic(Add(0));
  100.     addu(1) <= To_StdULogic(Add(1));
  101.     addu(2) <= To_StdULogic(Add(2));
  102.     addu(3) <= To_StdULogic(Add(3));
  103.     addu(4) <= To_StdULogic(Add(4));
  104.     addu(5) <= To_StdULogic(Add(5));
  105.     addu(6) <= To_StdULogic(Add(6));
  106.     addu(7) <= To_StdULogic(Add(7));
  107.  
  108. -- Cálculo dos 4 endereços (inteiros) a serem lidos devido ao endereçamento por byte
  109.     add1 <= add0 + 1;
  110.     add2 <= add0 + 2;
  111.     add3 <= add0 + 3;
  112.     add0 <= CONV_INTEGER(addu);
  113.  
  114. -- Conversão dos endereços no formato STD_LOGIC_VECTOR
  115.     addS0 <= CONV_STD_LOGIC_VECTOR(add0, 8);
  116.     addS1 <= CONV_STD_LOGIC_VECTOR(add1, 8);
  117.     addS2 <= CONV_STD_LOGIC_VECTOR(add2, 8);
  118.     addS3 <= CONV_STD_LOGIC_VECTOR(add3, 8);
  119.  
  120.     -- Conversão do dado (entrada) no formato STD_LOGIC_VECTOR
  121.     datainS <= datain;
  122.  
  123.     wrS <= wr;
  124.  
  125.     clockS <= clock;
  126.  
  127.     -- Conversão de dado (saída) para bit_vector
  128.     dataout <= dataoutS;
  129.  
  130. -- Distribuição dos vetores de dados para os bancos de memória
  131.     process (Sizein, datainS, datainS0, datainS1, datainS2, datainS3, dataoutS, dataoutS0, dataoutS1, dataoutS2, dataoutS3) begin
  132.         case Sizein is
  133.             when "00" =>
  134.                 datainS3 <= datainS(7  downto 0);
  135.                 datainS2 <= datainS2;
  136.                 datainS1 <= datainS1;
  137.                 datainS0 <= datainS0;
  138.  
  139.                 dataoutS(7  downto 0) <= dataoutS0;
  140.                 dataoutS(31 downto 8) <= "000000000000000000000000";
  141.             when "01" =>
  142.                 datainS3 <= datainS(7  downto 0);
  143.                 datainS2 <= datainS(15 downto 8);
  144.                 datainS1 <= datainS1;
  145.                 datainS0 <= datainS0;
  146.  
  147.                 dataoutS(7  downto 0)  <= dataoutS1;
  148.                 dataoutS(15 downto 8)  <= dataoutS0;
  149.                 dataoutS(31 downto 16) <= "0000000000000000";
  150.             when "10" =>
  151.                 datainS3 <= datainS(7  downto 0);
  152.                 datainS2 <= datainS(15 downto 8);
  153.                 datainS1 <= datainS(23 downto 16);
  154.                 datainS0 <= datainS(31 downto 24);
  155.  
  156.                 dataoutS(7  downto 0)  <= dataoutS3;
  157.                 dataoutS(15 downto 8)  <= dataoutS2;
  158.                 dataoutS(23 downto 16) <= dataoutS1;
  159.                 dataoutS(31 downto 24) <= dataoutS0;
  160.             when others =>
  161.         end case;
  162.     end process;
  163.  
  164. -- Bancos de memórias (cada banco possui 256 bytes)
  165.     MEM: lpm_ram_dq
  166.     GENERIC MAP (lpm_widthad => ADDR_WIDTH, lpm_width => DATA_WIDTH, lpm_file => INIT_FILE)
  167.     PORT MAP (data => datainS0, Address => addS0, we => wrS, inclock => clockS, outclock => clockS, q => dataoutS0);
  168.  
  169.     MEM_plus_One: lpm_ram_dq
  170.     GENERIC MAP (lpm_widthad => ADDR_WIDTH, lpm_width => DATA_WIDTH, lpm_file => INIT_FILE)
  171.     PORT MAP (data => datainS1, Address => addS1, we => wrS, inclock => clockS, outclock => clockS, q => dataoutS1);
  172.  
  173.     MEM_plus_Two: lpm_ram_dq
  174.     GENERIC MAP (lpm_widthad => ADDR_WIDTH, lpm_width => DATA_WIDTH, lpm_file => INIT_FILE)
  175.     PORT MAP (data => datainS2, Address => addS2, we => wrS, inclock => clockS, outclock => clockS, q => dataoutS2);
  176.  
  177.     MEM_plus_Three: lpm_ram_dq
  178.     GENERIC MAP (lpm_widthad => ADDR_WIDTH, lpm_width => DATA_WIDTH, lpm_file => INIT_FILE)
  179.     PORT MAP (data => datainS3, Address => addS3, we => wrS, inclock => clockS, outclock => clockS, q => dataoutS3);
  180.  
  181. END behavioral_arch;
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