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mx6qdl-sabreauto.dtsi

Nov 28th, 2019
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  1. /*
  2. * Copyright 2012-2015 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12.  
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/input/input.h>
  15.  
  16. / {
  17. aliases {
  18. mxcfb0 = &mxcfb1;
  19. mxcfb1 = &mxcfb2;
  20. mxcfb2 = &mxcfb3;
  21. mxcfb3 = &mxcfb4;
  22. };
  23.  
  24. memory: memory {
  25. reg = <0x10000000 0x80000000>;
  26. };
  27.  
  28. wlan_en_reg: fixedregulator@2 { /*WIFI*/
  29. compatible = "regulator-fixed";
  30. regulator-name = "wlan-en-regulator";
  31. regulator-min-microvolt = <1800000>;
  32. regulator-max-microvolt = <1800000>;
  33.  
  34. /* WLAN_EN GPIO for this board – Bank5, pin8 */
  35. gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
  36.  
  37. /* WLAN card specific delay */
  38. startup-delay-us = <70000>;
  39. enable-active-high;
  40. };
  41.  
  42. btwilink { /*BT*/
  43. compatible = "btwilink";
  44. };
  45.  
  46. kim {
  47. compatible = "kim";
  48. nshutdown_gpio = <135>; /* GPIO5_07 */ /* so its userspace number is (5 - 1) * 32 + 7 = 135 */
  49. dev_name = "/dev/ttymxc0";
  50. flow_cntrl = <1>;
  51. baud_rate = <3000000>;
  52. };
  53.  
  54. leds {
  55. compatible = "gpio-leds";
  56. pinctrl-names = "default";
  57. pinctrl-0 = <&pinctrl_gpio_leds>;
  58.  
  59. user {
  60. label = "debug";
  61. gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  62. };
  63. };
  64.  
  65. clocks {
  66. codec_osc: anaclk2 {
  67. compatible = "fixed-clock";
  68. #clock-cells = <0>;
  69. clock-frequency = <24576000>;
  70. };
  71. };
  72.  
  73. regulators {
  74. compatible = "simple-bus";
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77.  
  78. reg_audio: regulator@0 {
  79. compatible = "regulator-fixed";
  80. reg = <0>;
  81. regulator-name = "cs42888_supply";
  82. regulator-min-microvolt = <3300000>;
  83. regulator-max-microvolt = <3300000>;
  84. regulator-always-on;
  85. };
  86.  
  87. reg_3p3v: 3p3v {
  88. compatible = "regulator-fixed";
  89. regulator-name = "3P3V";
  90. regulator-min-microvolt = <3300000>;
  91. regulator-max-microvolt = <3300000>;
  92. regulator-always-on;
  93. };
  94.  
  95. reg_usb_h1_vbus: regulator@1 {
  96. compatible = "regulator-fixed";
  97. reg = <1>;
  98. regulator-name = "usb_h1_vbus";
  99. regulator-min-microvolt = <5000000>;
  100. regulator-max-microvolt = <5000000>;
  101. gpio = <&max7310_c 7 GPIO_ACTIVE_HIGH>;
  102. enable-active-high;
  103. };
  104.  
  105. reg_usb_otg_vbus: regulator@2 {
  106. compatible = "regulator-fixed";
  107. reg = <2>;
  108. regulator-name = "usb_otg_vbus";
  109. regulator-min-microvolt = <5000000>;
  110. regulator-max-microvolt = <5000000>;
  111. gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
  112. enable-active-high;
  113. };
  114.  
  115. reg_si4763_vio1: regulator@3 {
  116. compatible = "regulator-fixed";
  117. reg = <3>;
  118. regulator-name = "vio1";
  119. regulator-min-microvolt = <3300000>;
  120. regulator-max-microvolt = <3300000>;
  121. regulator-always-on;
  122. };
  123.  
  124. reg_si4763_vio2: regulator@4 {
  125. compatible = "regulator-fixed";
  126. reg = <4>;
  127. regulator-name = "vio2";
  128. regulator-min-microvolt = <3300000>;
  129. regulator-max-microvolt = <3300000>;
  130. regulator-always-on;
  131. };
  132.  
  133. reg_si4763_vd: regulator@5 {
  134. compatible = "regulator-fixed";
  135. reg = <5>;
  136. regulator-name = "vd";
  137. regulator-min-microvolt = <3300000>;
  138. regulator-max-microvolt = <3300000>;
  139. regulator-always-on;
  140. };
  141.  
  142. reg_si4763_va: regulator@6 {
  143. compatible = "regulator-fixed";
  144. reg = <6>;
  145. regulator-name = "va";
  146. regulator-min-microvolt = <5000000>;
  147. regulator-max-microvolt = <5000000>;
  148. regulator-always-on;
  149. };
  150.  
  151. reg_sd3_vmmc: regulator@7 {
  152. compatible = "regulator-fixed";
  153. regulator-name = "P3V3_SDa_SWITCHED";
  154. regulator-min-microvolt = <3300000>;
  155. regulator-max-microvolt = <3300000>;
  156. gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  157. enable-active-high;
  158. off-on-delay = <20000>;
  159. /* remove below line to enable this regulator */
  160. status = "disabled";
  161. };
  162.  
  163. reg_can_en: regulator@8 {
  164. compatible = "regulator-fixed";
  165. reg = <8>;
  166. regulator-name = "can-en";
  167. regulator-min-microvolt = <3300000>;
  168. regulator-max-microvolt = <3300000>;
  169. gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
  170. enable-active-high;
  171. };
  172.  
  173. reg_can_stby: regulator@9 {
  174. compatible = "regulator-fixed";
  175. reg = <9>;
  176. regulator-name = "can-stby";
  177. regulator-min-microvolt = <3300000>;
  178. regulator-max-microvolt = <3300000>;
  179. gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
  180. enable-active-high;
  181. vin-supply = <&reg_can_en>;
  182. };
  183. };
  184.  
  185. sound-hdmi {
  186. compatible = "fsl,imx6q-audio-hdmi",
  187. "fsl,imx-audio-hdmi";
  188. model = "imx-audio-hdmi";
  189. hdmi-controller = <&hdmi_audio>;
  190. };
  191.  
  192. mxcfb1: fb@0 {
  193. compatible = "fsl,mxc_sdc_fb";
  194. disp_dev = "ldb";
  195. interface_pix_fmt = "RGB666";
  196. default_bpp = <16>;
  197. int_clk = <0>;
  198. late_init = <0>;
  199. status = "disabled";
  200. };
  201.  
  202. mxcfb2: fb@1 {
  203. compatible = "fsl,mxc_sdc_fb";
  204. disp_dev = "hdmi";
  205. interface_pix_fmt = "RGB24";
  206. mode_str ="1920x1080M@60";
  207. default_bpp = <24>;
  208. int_clk = <0>;
  209. late_init = <0>;
  210. status = "disabled";
  211. };
  212.  
  213. mxcfb3: fb@2 {
  214. compatible = "fsl,mxc_sdc_fb";
  215. disp_dev = "lcd";
  216. interface_pix_fmt = "RGB565";
  217. mode_str ="CLAA-WVGA";
  218. default_bpp = <16>;
  219. int_clk = <0>;
  220. late_init = <0>;
  221. status = "disabled";
  222. };
  223.  
  224. mxcfb4: fb@3 {
  225. compatible = "fsl,mxc_sdc_fb";
  226. disp_dev = "ldb";
  227. interface_pix_fmt = "RGB666";
  228. default_bpp = <16>;
  229. int_clk = <0>;
  230. late_init = <0>;
  231. status = "disabled";
  232. };
  233.  
  234. clocks {
  235. codec_osc: anaclk2 {
  236. compatible = "fixed-clock";
  237. #clock-cells = <0>;
  238. clock-frequency = <24576000>;
  239. };
  240. };
  241.  
  242. sound-cs42888 {
  243. compatible = "fsl,imx6-sabreauto-cs42888",
  244. "fsl,imx-audio-cs42888";
  245. model = "imx-cs42888";
  246. esai-controller = <&esai>;
  247. asrc-controller = <&asrc>;
  248. audio-codec = <&codec>;
  249. status = "okay";
  250. };
  251.  
  252. sound-fm {
  253. compatible = "fsl,imx-audio-si476x",
  254. "fsl,imx-tuner-si476x";
  255. model = "imx-radio-si4763";
  256. ssi-controller = <&ssi2>;
  257. fm-controller = <&si476x_codec>;
  258. mux-int-port = <2>;
  259. mux-ext-port = <5>;
  260. };
  261.  
  262. sound-spdif {
  263. compatible = "fsl,imx-audio-spdif",
  264. "fsl,imx-sabreauto-spdif";
  265. model = "imx-spdif";
  266. spdif-controller = <&spdif>;
  267. spdif-in;
  268. };
  269.  
  270.  
  271. v4l2_cap_0 {
  272. compatible = "fsl,imx6q-v4l2-capture";
  273. ipu_id = <0>;
  274. csi_id = <0>;
  275. mclk_source = <0>;
  276. status = "okay";
  277. };
  278.  
  279. v4l2_out {
  280. compatible = "fsl,mxc_v4l2_output";
  281. status = "okay";
  282. };
  283. };
  284.  
  285. &audmux {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_audmux>;
  288. status = "okay";
  289. };
  290.  
  291. &clks {
  292. assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
  293. <&clks IMX6QDL_PLL4_BYPASS>,
  294. <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  295. <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
  296. <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
  297. assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
  298. <&clks IMX6QDL_PLL4_BYPASS_SRC>,
  299. <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
  300. <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  301. assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
  302. };
  303.  
  304. &dcic1 {
  305. dcic_id = <0>;
  306. dcic_mux = "dcic-hdmi";
  307. status = "okay";
  308. };
  309.  
  310. &dcic2 {
  311. dcic_id = <1>;
  312. dcic_mux = "dcic-lvds0";
  313. status = "okay";
  314. };
  315.  
  316. &ecspi1 {
  317. fsl,spi-num-chipselects = <1>;
  318. cs-gpios = <&gpio3 19 0>;
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  321. status = "disabled"; /* pin conflict with WEIM NOR */
  322.  
  323. flash: m25p80@0 {
  324. #address-cells = <1>;
  325. #size-cells = <1>;
  326. compatible = "st,m25p32", "jedec,spi-nor";
  327. spi-max-frequency = <20000000>;
  328. reg = <0>;
  329. };
  330. };
  331.  
  332. &esai {
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pinctrl_esai>;
  335. assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
  336. <&clks IMX6QDL_CLK_ESAI_EXTAL>;
  337. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  338. assigned-clock-rates = <0>, <24576000>;
  339. status = "okay";
  340. };
  341.  
  342. &gpmi {
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_gpmi_nand>;
  345. status = "disabled"; /* pin conflict with uart3 */
  346. nand-on-flash-bbt;
  347. };
  348.  
  349. &hdmi_audio {
  350. status = "okay";
  351. };
  352.  
  353. &hdmi_cec {
  354. pinctrl-names = "default";
  355. pinctrl-0 = <&pinctrl_hdmi_cec>;
  356. status = "okay";
  357. };
  358.  
  359. &hdmi_core {
  360. ipu_id = <0>;
  361. disp_id = <1>;
  362. status = "okay";
  363. };
  364.  
  365. &hdmi_video {
  366. fsl,phy_reg_vlev = <0x0294>;
  367. fsl,phy_reg_cksymtx = <0x800d>;
  368. status = "okay";
  369. };
  370.  
  371. &i2c1 {
  372. clock-frequency = <100000>;
  373. pinctrl-names = "default";
  374. pinctrl-0 = <&pinctrl_i2c1>;
  375. status = "okay";
  376.  
  377. /* LSM330DLCTR - ACCELEROMETER/GYROSCOPE */
  378. lsm330dlc-accel@19 {
  379. compatible = "st,lsm330dlc-accel";
  380. reg = <0x19>;
  381. interrupt-parent = <&gpio6>; /* EIM_BCLK__GPIO6_IO31 -int_accel */
  382. interrupts = <31 1>;
  383. };
  384.  
  385. lsm330dlc-gyro@6b {
  386. compatible = "st,lsm330dlc-gyro";
  387. reg = <0x6b>;
  388. pinctrl-assert-gpios = <&max7310_c 6 GPIO_ACTIVE_HIGH>, <&max7310_c 4 GPIO_ACTIVE_LOW>, <&tca6408_u20 0 GPIO_ACTIVE_LOW>, <&tca6408_u20 3 GPIO_ACTIVE_LOW>, <&max7310_a 5 GPIO_ACTIVE_HIGH>;
  389. interrupt-parent = <&gpio3>; /* EIM_DA13__GPIO3_IO13 -int_gryo */
  390. interrupts = <13 1>;
  391. };
  392.  
  393. };
  394.  
  395. &i2c2 {
  396. clock-frequency = <100000>;
  397. pinctrl-names = "default";
  398. pinctrl-0 = <&pinctrl_i2c2>;
  399. status = "okay";
  400.  
  401. codec: cs42888@48 {
  402. compatible = "cirrus,cs42888";
  403. reg = <0x48>;
  404. clocks = <&codec_osc>;
  405. clock-names = "mclk";
  406. VA-supply = <&reg_audio>;
  407. VD-supply = <&reg_audio>;
  408. VLS-supply = <&reg_audio>;
  409. VLC-supply = <&reg_audio>;
  410. status = "okay";
  411. };
  412.  
  413. pmic: pfuze100@08 {
  414. compatible = "fsl,pfuze100";
  415. reg = <0x08>;
  416.  
  417. regulators {
  418. sw1a_reg: sw1ab {
  419. regulator-min-microvolt = <300000>;
  420. regulator-max-microvolt = <1875000>;
  421. regulator-boot-on;
  422. regulator-always-on;
  423. regulator-ramp-delay = <6250>;
  424. };
  425.  
  426. sw1c_reg: sw1c {
  427. regulator-min-microvolt = <300000>;
  428. regulator-max-microvolt = <1875000>;
  429. regulator-boot-on;
  430. regulator-always-on;
  431. regulator-ramp-delay = <6250>;
  432. };
  433.  
  434. sw2_reg: sw2 {
  435. regulator-min-microvolt = <800000>;
  436. regulator-max-microvolt = <3300000>;
  437. regulator-boot-on;
  438. regulator-always-on;
  439. };
  440.  
  441. sw3a_reg: sw3a {
  442. regulator-min-microvolt = <400000>;
  443. regulator-max-microvolt = <1975000>;
  444. regulator-boot-on;
  445. regulator-always-on;
  446. };
  447.  
  448. sw3b_reg: sw3b {
  449. regulator-min-microvolt = <400000>;
  450. regulator-max-microvolt = <1975000>;
  451. regulator-boot-on;
  452. regulator-always-on;
  453. };
  454.  
  455. sw4_reg: sw4 {
  456. regulator-min-microvolt = <800000>;
  457. regulator-max-microvolt = <3300000>;
  458. };
  459.  
  460. swbst_reg: swbst {
  461. regulator-min-microvolt = <5000000>;
  462. regulator-max-microvolt = <5150000>;
  463. };
  464.  
  465. snvs_reg: vsnvs {
  466. regulator-min-microvolt = <1000000>;
  467. regulator-max-microvolt = <3000000>;
  468. regulator-boot-on;
  469. regulator-always-on;
  470. };
  471.  
  472. vref_reg: vrefddr {
  473. regulator-boot-on;
  474. regulator-always-on;
  475. };
  476.  
  477. vgen1_reg: vgen1 {
  478. regulator-min-microvolt = <800000>;
  479. regulator-max-microvolt = <1550000>;
  480. };
  481.  
  482. vgen2_reg: vgen2 {
  483. regulator-min-microvolt = <800000>;
  484. regulator-max-microvolt = <1550000>;
  485. };
  486.  
  487. vgen3_reg: vgen3 {
  488. regulator-min-microvolt = <1800000>;
  489. regulator-max-microvolt = <3300000>;
  490. };
  491.  
  492. vgen4_reg: vgen4 {
  493. regulator-min-microvolt = <1800000>;
  494. regulator-max-microvolt = <3300000>;
  495. regulator-always-on;
  496. };
  497.  
  498. vgen5_reg: vgen5 {
  499. regulator-min-microvolt = <1800000>;
  500. regulator-max-microvolt = <3300000>;
  501. regulator-always-on;
  502. };
  503.  
  504. vgen6_reg: vgen6 {
  505. regulator-min-microvolt = <1800000>;
  506. regulator-max-microvolt = <3300000>;
  507. regulator-always-on;
  508. };
  509. };
  510. };
  511.  
  512. hdmi_edid: edid@50 {
  513. compatible = "fsl,imx6-hdmi-i2c";
  514. reg = <0x50>;
  515. };
  516.  
  517.  
  518. si4763: si4763@63 {
  519. compatible = "si4761";
  520. reg = <0x63>;
  521. va-supply = <&reg_si4763_va>;
  522. vd-supply = <&reg_si4763_vd>;
  523. vio1-supply = <&reg_si4763_vio1>;
  524. vio2-supply = <&reg_si4763_vio2>;
  525. revision-a10; /* set to default A10 compatible command set */
  526.  
  527. si476x_codec: si476x-codec {
  528. compatible = "si476x-codec";
  529. };
  530. };
  531. };
  532.  
  533. &i2c3 {
  534. pinctrl-names = "default", "sleep";
  535. pinctrl-0 = <&pinctrl_i2c3 &pinctrl_focaltech>;
  536. pinctrl-1 = <&pinctrl_i2c3 &pinctrl_focaltech>;
  537. status = "okay";
  538.  
  539.  
  540. focaltech@38{
  541. compatible = "focaltech,fts";
  542. reg = <0x38>;
  543. interrupt-parent = <&gpio2>;
  544. interrupts = <28 0x02>;
  545. focaltech,panel-type = <FT5426>;
  546. focaltech,reset-gpio = <&gpio1 8 0x01>;
  547. focaltech,irq-gpio = <&gpio2 28 0x02>;
  548. focaltech,max-touch-number = <5>;
  549. focaltech,display-coords = <0 0 1020 596>;
  550.  
  551. focaltech,have-key;
  552. focaltech,key-number = <3>;
  553. focaltech,keys = <139 102 158>;
  554. focaltech,key-y-coord = <2000>;
  555. focaltech,key-x-coords = <200 600 800>;
  556. };
  557.  
  558. adv7180: adv7180@21 {
  559. compatible = "adv,adv7180";
  560. reg = <0x21>;
  561. pinctrl-names = "default";
  562. pinctrl-0 = <&pinctrl_ipu1_1>;
  563. clocks = <&clks IMX6QDL_CLK_CKO>;
  564. clock-names = "csi_mclk";
  565. DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
  566. AVDD-supply = <&reg_3p3v>; /* 1.8v */
  567. DVDD-supply = <&reg_3p3v>; /* 1.8v */
  568. PVDD-supply = <&reg_3p3v>; /* 1.8v */
  569. pwn-gpios = <&max7310_c 3 0>;
  570. csi_id = <0>;
  571. mclk = <24000000>;
  572. mclk_source = <0>;
  573. cvbs = <1>;
  574. };
  575.  
  576. isl29023@44 {
  577. compatible = "fsl,isl29023";
  578. reg = <0x44>;
  579. rext = <499>;
  580. interrupt-parent = <&gpio5>;
  581. interrupts = <17 2>;
  582. };
  583.  
  584. tca6408_u20: gpio@20 {
  585. compatible = "ti,tca6408";
  586. reg = <0x20>;
  587. gpio-controller;
  588. #gpio-cells = <2>;
  589. };
  590.  
  591. max7310_a: gpio@30 {
  592. compatible = "maxim,max7310";
  593. reg = <0x30>;
  594. gpio-controller;
  595. #gpio-cells = <2>;
  596. };
  597.  
  598. max7310_b: gpio@32 {
  599. compatible = "maxim,max7310";
  600. reg = <0x32>;
  601. gpio-controller;
  602. #gpio-cells = <2>;
  603. };
  604.  
  605. max7310_c: gpio@34 {
  606. compatible = "maxim,max7310";
  607. reg = <0x34>;
  608. gpio-controller;
  609. #gpio-cells = <2>;
  610. };
  611.  
  612. mag3110@0e {
  613. compatible = "fsl,mag3110";
  614. reg = <0x0e>;
  615. position = <2>;
  616. interrupt-parent = <&gpio2>;
  617. interrupts = <29 1>;
  618. };
  619.  
  620. mma8451@1c {
  621. compatible = "fsl,mma8451";
  622. reg = <0x1c>;
  623. position = <7>;
  624. interrupt-parent = <&gpio6>;
  625. interrupts = <31 8>;
  626. interrupt-route = <1>;
  627. };
  628. };
  629.  
  630. &iomuxc {
  631. pinctrl-names = "default";
  632. pinctrl-0 = <&pinctrl_hog>;
  633.  
  634. imx6qdl-sabreauto {
  635. pinctrl_audmux: audmux {
  636. fsl,pins = <
  637. MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
  638. MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
  639. MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
  640. >;
  641. };
  642.  
  643. pinctrl_hog: hoggrp {
  644. fsl,pins = <
  645. /*MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059*/
  646. /*MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000*/
  647. /*MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 */
  648. /*MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000*/
  649. MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x13059
  650. MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000
  651. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
  652. /*MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000*/
  653. /*MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 */
  654. MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
  655. /* MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 */
  656. /*MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 */
  657. >;
  658. };
  659.  
  660. pinctrl_ecspi1: ecspi1grp {
  661. fsl,pins = <
  662. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  663. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  664. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  665. >;
  666. };
  667.  
  668. pinctrl_ecspi1_cs: ecspi1cs {
  669. fsl,pins = <
  670. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  671. >;
  672. };
  673.  
  674. pinctrl_focaltech: focaltechgrp {
  675. fsl,pins = <
  676. MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* Interrupt */
  677. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Reset */
  678. >;
  679. };
  680.  
  681. pinctrl_esai: esaigrp {
  682. fsl,pins = <
  683. MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
  684. MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
  685. MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
  686. MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
  687. MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
  688. MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
  689. MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
  690. MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
  691. MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
  692. MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
  693. >;
  694. };
  695.  
  696. pinctrl_gpio_leds: gpioledsgrp {
  697. fsl,pins = <
  698. MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
  699. >;
  700. };
  701.  
  702. pinctrl_gpmi_nand: gpminandgrp {
  703. fsl,pins = <
  704. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  705. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  706. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  707. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  708. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  709. MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  710. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  711. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  712. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  713. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  714. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  715. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  716. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  717. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  718. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  719. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  720. MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  721. >;
  722. };
  723.  
  724. pinctrl_i2c1: i2c1grp {
  725. fsl,pins = <
  726. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  727. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  728. >;
  729. };
  730.  
  731. pinctrl_i2c2: i2c2grp {
  732. fsl,pins = <
  733. MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
  734. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  735. >;
  736. };
  737.  
  738. pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
  739. fsl,pins = <
  740. MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
  741. MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
  742. MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
  743. MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
  744. MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
  745. MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
  746. MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
  747. MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
  748. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  749. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  750. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  751. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  752. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  753. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  754. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  755. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  756. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  757. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  758. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  759. >;
  760. };
  761.  
  762. pinctrl_i2c3: i2c3grp {
  763. fsl,pins = <
  764. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  765. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  766. >;
  767. };
  768.  
  769.  
  770. pinctrl_spdif: spdifgrp {
  771. fsl,pins = <
  772. MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
  773. >;
  774. };
  775.  
  776. pinctrl_uart1_1: uart1grp-1 {
  777. fsl,pins = <
  778. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 // used for HOST_HCI_RX
  779. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 // used for HOST_HCI_TX
  780. MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
  781. MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
  782. >;
  783. };
  784. pinctrl_uart2_1: uart2grp-1 {
  785. fsl,pins = <
  786. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  787. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  788. >;
  789. };
  790.  
  791. pinctrl_uart3_1: uart3grp-1 {
  792. fsl,pins = <
  793. MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
  794. MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
  795. MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
  796. MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  797. >;
  798. };
  799.  
  800. pinctrl_uart3dte_1: uart3dtegrp-1 {
  801. fsl,pins = <
  802. MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
  803. MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
  804. MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
  805. MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
  806. >;
  807. };
  808.  
  809. pinctrl_uart4: uart4grp {
  810. fsl,pins = <
  811. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  812. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  813. >;
  814. };
  815.  
  816.  
  817. pinctrl_uart5: uart5grp {
  818. fsl,pins = <
  819. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  820. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  821. MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
  822. MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
  823. >;
  824. };
  825.  
  826. pinctrl_usbotg: usbotggrp {
  827. fsl,pins = <
  828. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  829. >;
  830. };
  831.  
  832. pinctrl_usdhc1: usdhc1grp {
  833. fsl,pins = <
  834. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069
  835. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10069
  836. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
  837. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
  838. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
  839. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
  840. MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x13059 // reserve two pins wl8 gpio, this is pulled low at reset for WL_EN
  841. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x13059 // this is for WL_IRQ which driver will configure as an input with a pull down
  842. >;
  843. };
  844.  
  845. pinctrl_usdhc2: usdhc2grp {
  846. fsl,pins = <
  847. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  848. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  849. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  850. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  851. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  852. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  853. MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
  854. MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
  855. MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
  856. MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
  857. >;
  858. };
  859.  
  860. pinctrl_usdhc3: usdhc3grp {
  861. fsl,pins = <
  862. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  863. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  864. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  865. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  866. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  867. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  868. >;
  869. };
  870.  
  871. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  872. fsl,pins = <
  873. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  874. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  875. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  876. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  877. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  878. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  879. >;
  880. };
  881.  
  882. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  883. fsl,pins = <
  884. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  885. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  886. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  887. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  888. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  889. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  890.  
  891. >;
  892. };
  893.  
  894. pinctrl_hdmi_cec: hdmicecgrp {
  895. fsl,pins = <
  896. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  897. >;
  898. };
  899. };
  900. };
  901.  
  902. &ldb {
  903. status = "okay";
  904.  
  905. lvds-channel@0 {
  906. fsl,data-mapping = "spwg";
  907. fsl,data-width = <24>;
  908. primary;
  909. status = "okay";
  910.  
  911. display-timings {
  912. native-mode = <&timing0>;
  913. timing0: hsd100pxn1 {
  914. clock-frequency = <51200000>;
  915. hactive = <1024>;
  916. vactive = <600>;
  917. hback-porch = <220>;
  918. hfront-porch = <40>;
  919. vback-porch = <20>;
  920. vfront-porch = <5>;
  921. hsync-len = <60>;
  922. vsync-len = <10>;
  923. };
  924. };
  925. };
  926.  
  927. lvds-channel@1 {
  928. fsl,data-mapping = "spwg";
  929. fsl,data-width = <24>;
  930. status = "okay";
  931.  
  932. display-timings {
  933. native-mode = <&timing1>;
  934. timing1: hsd100pxn1 {
  935. clock-frequency = <51200000>;
  936. hactive = <1024>;
  937. vactive = <600>;
  938. hback-porch = <220>;
  939. hfront-porch = <40>;
  940. vback-porch = <20>;
  941. vfront-porch = <5>;
  942. hsync-len = <60>;
  943. vsync-len = <10>;
  944. };
  945. };
  946. };
  947. };
  948.  
  949. &pcie {
  950. status = "okay";
  951. };
  952.  
  953. &spdif {
  954. pinctrl-names = "default";
  955. pinctrl-0 = <&pinctrl_spdif>;
  956. assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>,
  957. <&clks IMX6QDL_CLK_SPDIF_PODF>;
  958. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>;
  959. assigned-clock-rates = <0>, <227368421>;
  960. status = "okay";
  961. };
  962.  
  963. &snvs_poweroff {
  964. status = "okay";
  965. };
  966.  
  967. &ssi2 {
  968. assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
  969. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  970. assigned-clock-rates = <0>;
  971. fsl,mode = "i2s-master";
  972. status = "okay";
  973. };
  974.  
  975. /* Bluetooth Uart */
  976. &uart1 {
  977. pinctrl-names = "default";
  978. pinctrl-0 = <&pinctrl_uart1_1>;
  979. fsl,uart-has-rtscts;
  980. status = "okay";
  981. };
  982.  
  983. /* ttymxc1 UART - GNSS */
  984. &uart2 {
  985. pinctrl-names = "default";
  986. pinctrl-0 = <&pinctrl_uart2_1>;
  987. status = "okay";
  988. };
  989.  
  990. /* OBD */
  991. &uart3 {
  992. pinctrl-names = "default";
  993. pinctrl-0 = <&pinctrl_uart3_1>;
  994. fsl,uart-has-rtscts;
  995. status = "okay";
  996. /* for DTE mode, add below change */
  997. /* fsl,dte-mode; */
  998. /* pinctrl-0 = <&pinctrl_uart3dte_1>; */
  999. };
  1000.  
  1001. /* Console Uart */
  1002. &uart4 {
  1003. pinctrl-names = "default";
  1004. pinctrl-0 = <&pinctrl_uart4>;
  1005. status = "okay";
  1006. };
  1007.  
  1008. /* RS232 Uart */
  1009. &uart5 {
  1010. pinctrl-names = "default";
  1011. pinctrl-0 = <&pinctrl_uart5>;
  1012. fsl,uart-has-rtscts;
  1013. status = "okay";
  1014. };
  1015.  
  1016. &usbh1 {
  1017. vbus-supply = <&reg_usb_h1_vbus>;
  1018. status = "okay";
  1019. };
  1020.  
  1021. &usbotg {
  1022. vbus-supply = <&reg_usb_otg_vbus>;
  1023. pinctrl-names = "default";
  1024. pinctrl-0 = <&pinctrl_usbotg>;
  1025. srp-disable;
  1026. hnp-disable;
  1027. adp-disable;
  1028. status = "okay";
  1029. };
  1030.  
  1031. &usdhc1 { /*WIFI*/
  1032. pinctrl-names = "default";
  1033. pinctrl-0 = <&pinctrl_usdhc1>;
  1034. bus-width = <4>;
  1035. no-1-8-v;
  1036. keep-power-in-suspend;
  1037. enable-sdio-wakeup;
  1038. vmmc-supply = <&wlan_en_reg>;
  1039. non-removable; /* non-removable is not a variable, the fact it is */
  1040. /* listed is all that is used by driver */
  1041. cap-power-off-card;
  1042. status = "okay";
  1043. #address-cells = <1>;
  1044. #size-cells = <0>;
  1045. wlcore: wlcore@0 {
  1046. compatible = "ti,wl1831";
  1047. reg = <2>;
  1048. interrupt-parent = <&gpio5>;
  1049. interrupts = <9 1>;
  1050. ref-clock-frequency = <38400000>;
  1051. tcxo-clock-frequency = <26000000>;
  1052. };
  1053. };
  1054.  
  1055. &usdhc2 {
  1056. pinctrl-names = "default";
  1057. pinctrl-0 = <&pinctrl_usdhc2>;
  1058. bus-width = <8>;
  1059. non-removable;
  1060. no-1-8-v;
  1061. keep-power-in-suspend;
  1062. status = "okay";
  1063. };
  1064.  
  1065. &usdhc3 {
  1066. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1067. pinctrl-0 = <&pinctrl_usdhc3>;
  1068. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  1069. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  1070. bus-width = <4>;
  1071. non-removable;
  1072. no-1-8-v;
  1073. /*
  1074. * Due to board issue, we can not use external regulator for card slot
  1075. * by default since the card power is shared with card detect pullup.
  1076. * Disabling the vmmc regulator will cause unexpected card detect
  1077. * interrupts.
  1078. * HW rework is needed to fix this isssue. Remove R695 first, then you
  1079. * can open below line to enable the using of external regulator.
  1080. * Then you will be able to power off the card during suspend. This is
  1081. * especially needed for a SD3.0 card re-enumeration working on UHS mode
  1082. * Note: reg_sd3_vmmc is also need to be enabled
  1083. */
  1084. /* vmmc-supply = <&reg_sd3_vmmc>; */
  1085. keep-power-in-suspend;
  1086. enable-sdio-wakeup;
  1087. status = "okay";
  1088. };
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