module Controle(input wire [5:0] Opcode,
input wire [5:0] func,
input wire [0:0] clk,
output reg [0:0] PCWrite,
output reg [0:0] PCWriteCond,
output reg [1:0] PCWriteCondMux,
output reg [2:0] MuxBranch,
output reg [2:0] MuxMemoriaEnd,
output reg [0:0] IRWrite,
output reg [0:0] RegWrite,
output reg [1:0] RegDst,
output reg [2:0] MuxULA1,
output reg [2:0] ALUControl,
output reg [0:0] ALUOutControl,
output reg [0:0] DivControl,
output reg [2:0] MuxULA2,
output reg [1:0] MuxMemoriaDado,
output reg [0:0] AControl,
output reg [0:0] BControl,
output reg [0:0] EPCCont,
output reg [0:0] MultControl,
output reg [2:0] RDControl,
output reg [0:0] MuxRD,
output reg [0:0] MuxSaidaLO,
output reg [0:0] MuxSaidaHI,
output reg [1:0] ContShifts,
output reg [3:0] MuxWriteData,
output reg [0:0] MuxHILO,
output reg [0:0] LuiControl,
output reg [0:0] MuxMDR,
output reg [2:0] ControleBits,
output reg [0:0] CHi,
output reg [0:0] CLo,
output reg [0:0] MemRead,
output reg [0:0] MDRControl);

reg [31:0] state;

	always @(posedge clk)begin

			case(state)
				//RESET
				32'b00000000000000000000000000000000:
				begin
					state <= 32'b00000000000000000000000000000001;
				end

				32'b00000000000000000000000000000001:
				begin
					RegDst <= 2'b11;
					RegWrite <= 1'd1;
					MuxWriteData <= 4'b1000;
					state <= 32'b00000000000000000000000000000010;
				end

				32'b00000000000000000000000000000010:
				begin
					RegWrite <= 1'd0;
					state <= 32'b00000000000000000000000000000011;
				end
				//PC+4
				32'b00000000000000000000000000000011:
				begin
					MuxULA1 <= 3'b000;
					MuxULA2 <= 3'b001;
					MuxMemoriaEnd <= 3'b000;
					ALUControl <= 3'b001;
					PCWrite <= 1'b1;
					MemRead <= 1'b0;
					state <= 32'b00000000000000000000000000000100;
				end

				32'b00000000000000000000000000000100:
				begin
					PCWrite <= 1'b0;
					state <= 32'b00000000000000000000000000000101;
				end

				32'b00000000000000000000000000000101:
				begin
					IRWrite <= 1'b1;
					state <= 32'b00000000000000000000000000000110;
				end
		endcase
	end
endmodule