module AND(x,y,z);
	input x,y;
	output z;
	reg z;

	always @(x,y,z) begin
		z = x & y;
	end
endmodule

module NAND(x,y,z);
	input x,y;
	output z;
	reg z;

	always @(x,y,z) begin
		z = !(x & y);
	end
endmodule

module SHIFT_LEFT(shift, in, out);
	input[4:0] shift;
	input[15:0] in;
	output[15:0] out;
	reg[15:0] out;

	always @(shift, in, out) begin
		out = in << shift;
	end
endmodule