module ram (address, data, CS, WE, OE);

    parameter AddressSize  = 1;
    parameter WordSize = 1;

    input wire[AddressSize-1:0] address;
    input wire[WordSize-1:0] data;
    input wire CS,WE,OE;

    reg [WordSize-1:0] Mem[0:(1<<AddressSize)-1];

    assign data = (!CS && !OE) ? Mem[address]:{WordSize{1'bz}};


    always @ (CS or WE) //ïðîöåññ çàïèñè â ÿ÷åéêó ïàìÿòè
        begin
            if (!CS && !WE)
                Mem[address] = data;
        end

    always @ (WE or OE) //ïðîöåññ ñ÷èòûâíèÿ äàííûõ
        begin

        end

endmodule