device tree

/dts-v1/;

/ {
	interrupt-parent = <0x1>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Mistral 820 Nanosom Starter Kit";
	compatible = "qcom,apq8096-nanosom";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x0>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		mba@91500000 {
			reg = <0x0 0x91500000 0x0 0x200000>;
			no-map;
			phandle = <0x9a>;
		};

		venus@90400000 {
			reg = <0x0 0x90400000 0x0 0x700000>;
			no-map;
			phandle = <0x95>;
		};

		adsp@8ea00000 {
			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
			no-map;
			phandle = <0xac>;
		};

		mpss@88800000 {
			reg = <0x0 0x88800000 0x0 0x6200000>;
			no-map;
			phandle = <0x9b>;
		};

		smem-mem@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
			phandle = <0x14>;
		};

		memory@85800000 {
			reg = <0x0 0x85800000 0x0 0x800000>;
			no-map;
		};

		memory@86200000 {
			reg = <0x0 0x86200000 0x0 0x2600000>;
			no-map;
		};

		rmtfs@86700000 {
			compatible = "qcom,rmtfs-mem";
			size = <0x0 0x200000>;
			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
			no-map;
			qcom,client-id = <0x1>;
			qcom,vmid = <0xf>;
		};

		gpu@8f200000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90b00000 0x0 0xa00000>;
			no-map;
			phandle = <0x89>;
		};
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <0x2 0x3 0x4 0x5>;
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x6>;
			phandle = <0x8>;

			l2-cache {
				compatible = "cache";
				cache-level = <0x2>;
				phandle = <0x6>;
			};
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x1>;
			enable-method = "psci";
			cpu-idle-states = <0x2 0x3 0x4 0x5>;
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x6>;
			phandle = <0x9>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <0x2 0x3 0x4 0x5>;
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x7>;
			phandle = <0xa>;

			l2-cache {
				compatible = "cache";
				cache-level = <0x2>;
				phandle = <0x7>;
			};
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x101>;
			enable-method = "psci";
			cpu-idle-states = <0x2 0x3 0x4 0x5>;
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x7>;
			phandle = <0xb>;
		};

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x8>;
				};

				core1 {
					cpu = <0x9>;
				};
			};

			cluster1 {

				core0 {
					cpu = <0xa>;
				};

				core1 {
					cpu = <0xb>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "wfi";
				arm,psci-suspend-param = <0x1>;
				entry-latency-us = <0x28>;
				exit-latency-us = <0x50>;
				min-residency-us = <0x12c>;
				phandle = <0x2>;
			};

			cpu-sleep-1 {
				compatible = "arm,idle-state";
				idle-state-name = "standalone-power-collapse";
				arm,psci-suspend-param = <0x4>;
				entry-latency-us = <0x82>;
				exit-latency-us = <0x50>;
				min-residency-us = <0x12c>;
				phandle = <0x3>;
			};

			cluster-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "pwr-l2-wfi";
				arm,psci-suspend-param = <0x40000001>;
				entry-latency-us = <0x2d>;
				exit-latency-us = <0x55>;
				min-residency-us = <0x12c>;
				phandle = <0x4>;
			};

			system-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "system-wfi";
				arm,psci-suspend-param = <0x40000001>;
				entry-latency-us = <0x14>;
				exit-latency-us = <0x78>;
				min-residency-us = <0x12c>;
				phandle = <0x5>;
			};
		};
	};

	thermal-zones {

		cpu0-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x3>;

			trips {

				trip-point@0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				cpu_crit {
					temperature = <0x1adb0>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x5>;

			trips {

				trip-point@0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				cpu_crit {
					temperature = <0x1adb0>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x8>;

			trips {

				trip-point@0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				cpu_crit {
					temperature = <0x1adb0>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0xa>;

			trips {

				trip-point@0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				cpu_crit {
					temperature = <0x1adb0>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};

		gpu-thermal-top {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x6>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		gpu-thermal-bottom {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x7>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		m4m-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x1>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		l3-or-venus-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x2>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		cluster0-l2-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0x7>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		cluster1-l2-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xc 0xc>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		camera-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x1>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		q6-dsp-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x2>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x3>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};

		modemtx-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0xd 0x4>;

			trips {

				trip-point@0 {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "hot";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
	};

	clocks {
		compatible = "simple-bus";

		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x124f800>;
			clock-output-names = "xo_board";
			phandle = <0x49>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x7ffc>;
			clock-output-names = "sleep_clk";
		};

		divclk4 {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x8000>;
			clock-output-names = "divclk4";
			pinctrl-names = "default";
			pinctrl-0 = <0xe>;
			phandle = <0x3c>;
		};

		divclk1 {
			compatible = "gpio-gate-clock";
			pinctrl-0 = <0xf>;
			pinctrl-names = "default";
			clocks = <0x10 0x2e>;
			#clock-cells = <0x0>;
			enable-gpios = <0x11 0xf 0x0>;
			phandle = <0x85>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	firmware {

		scm {
			compatible = "qcom,scm-msm8996";
			qcom,dload-mode = <0x12 0x13000>;
		};
	};

	hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <0x13 0x0 0x1000>;
		#hwlock-cells = <0x1>;
		phandle = <0x15>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <0x14>;
		hwlocks = <0x15 0x3>;
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";
		interrupts = <0x0 0xa8 0x1>;
		qcom,rpm-msg-ram = <0x16>;
		mboxes = <0x17 0x0>;

		rpm_requests {
			compatible = "qcom,rpm-msm8996";
			qcom,glink-channels = "rpm_requests";

			qcom,rpmcc {
				compatible = "qcom,rpmcc-msm8996";
				#clock-cells = <0x1>;
				phandle = <0x10>;
			};

			power-controller {
				compatible = "qcom,msm8996-rpmpd";
				#power-domain-cells = <0x1>;
				operating-points-v2 = <0x18>;

				opp-table {
					compatible = "operating-points-v2";
					phandle = <0x18>;

					opp1 {
						opp-level = <0x1>;
					};

					opp2 {
						opp-level = <0x2>;
					};

					opp3 {
						opp-level = <0x3>;
					};

					opp4 {
						opp-level = <0x4>;
					};

					opp5 {
						opp-level = <0x5>;
					};

					opp6 {
						opp-level = <0x6>;
					};
				};
			};

			pm8994-regulators {
				compatible = "qcom,rpm-pm8994-regulators";
				vdd_l1-supply = <0x19>;
				vdd_l2_l26_l28-supply = <0x19>;
				vdd_l3_l11-supply = <0x19>;
				vdd_l4_l27_l31-supply = <0x19>;
				vdd_l5_l7-supply = <0x1a>;
				vdd_l14_l15-supply = <0x1a>;
				vdd_l20_l21-supply = <0x1a>;
				vdd_l25-supply = <0x19>;

				s1 {
					phandle = <0x98>;
				};

				s2 {
					phandle = <0x97>;
				};

				s3 {
					regulator-min-microvolt = <0x13d620>;
					regulator-max-microvolt = <0x13d620>;
					phandle = <0x19>;
				};

				s4 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x62>;
				};

				s5 {
					regulator-min-microvolt = <0x20ce70>;
					regulator-max-microvolt = <0x20ce70>;
					phandle = <0x1a>;
				};

				s6 {
				};

				s7 {
					regulator-min-microvolt = <0xc3500>;
					regulator-max-microvolt = <0xc3500>;
				};

				s8 {
				};

				s9 {
				};

				s10 {
				};

				s11 {
				};

				s12 {
				};

				l1 {
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0xf4240>;
				};

				l2 {
					regulator-min-microvolt = <0x1312d0>;
					regulator-max-microvolt = <0x1312d0>;
					phandle = <0x6b>;
				};

				l3 {
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0xcf850>;
				};

				l4 {
					regulator-min-microvolt = <0x12b128>;
					regulator-max-microvolt = <0x12b128>;
				};

				l5 {
				};

				l6 {
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
				};

				l7 {
				};

				l8 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l9 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l10 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l11 {
					regulator-min-microvolt = <0x118c30>;
					regulator-max-microvolt = <0x118c30>;
				};

				l12 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x5d>;
				};

				l13 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x2d0370>;
					phandle = <0x54>;
				};

				l14 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l15 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l16 {
					regulator-min-microvolt = <0x2932e0>;
					regulator-max-microvolt = <0x2932e0>;
				};

				l17 {
					regulator-min-microvolt = <0x2625a0>;
					regulator-max-microvolt = <0x2625a0>;
				};

				l18 {
					regulator-min-microvolt = <0x2932e0>;
					regulator-max-microvolt = <0x2c4020>;
				};

				l19 {
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;
				};

				l20 {
					regulator-min-microvolt = <0x2d0370>;
					regulator-max-microvolt = <0x2d0370>;
					regulator-allow-set-load;
					phandle = <0x61>;
				};

				l21 {
					regulator-min-microvolt = <0x2d0370>;
					regulator-max-microvolt = <0x2d0370>;
					phandle = <0x53>;
				};

				l22 {
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					phandle = <0x8a>;
				};

				l23 {
					regulator-min-microvolt = <0x2ab980>;
					regulator-max-microvolt = <0x2ab980>;
				};

				l24 {
					regulator-min-microvolt = <0x2eebb8>;
					regulator-max-microvolt = <0x2eebb8>;
					phandle = <0x64>;
				};

				l25 {
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
					regulator-allow-set-load;
					phandle = <0x5e>;
				};

				l26 {
				};

				l27 {
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0xf4240>;
				};

				l28 {
					regulator-min-microvolt = <0xe1d48>;
					regulator-max-microvolt = <0xe1d48>;
					regulator-allow-set-load;
					phandle = <0x5c>;
				};

				l29 {
					regulator-min-microvolt = <0x2ab980>;
					regulator-max-microvolt = <0x2ab980>;
				};

				l30 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				l31 {
				};

				l32 {
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};
			};
		};
	};

	soc {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x0 0x0 0x0 0xffffffff>;
		compatible = "simple-bus";

		memory@68000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x68000 0x6000>;
			phandle = <0x16>;
		};

		rng@83000 {
			compatible = "qcom,prng-ee";
			reg = <0x83000 0x1000>;
			clocks = <0x1b 0x98>;
			clock-names = "core";
		};

		syscon@740000 {
			compatible = "syscon";
			reg = <0x740000 0x40000>;
			phandle = <0x13>;
		};

		thermal-sensor@4a9000 {
			compatible = "qcom,msm8996-tsens";
			reg = <0x4a9000 0x1000 0x4a8000 0x1000>;
			#qcom,sensors = <0xd>;
			#thermal-sensor-cells = <0x1>;
			phandle = <0xc>;
		};

		thermal-sensor@4ad000 {
			compatible = "qcom,msm8996-tsens";
			reg = <0x4ad000 0x1000 0x4ac000 0x1000>;
			#qcom,sensors = <0x8>;
			#thermal-sensor-cells = <0x1>;
			phandle = <0xd>;
		};

		syscon@7a0000 {
			compatible = "qcom,tcsr-msm8996", "syscon";
			reg = <0x7a0000 0x18000>;
			phandle = <0x12>;
		};

		interrupt-controller@9bc0000 {
			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
			#interrupt-cells = <0x3>;
			interrupt-controller;
			#redistributor-regions = <0x1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x9bc0000 0x10000 0x9c00000 0x100000>;
			interrupts = <0x1 0x9 0x4>;
			phandle = <0x1>;
		};

		mailbox@9820000 {
			compatible = "qcom,msm8996-apcs-hmss-global";
			reg = <0x9820000 0x1000>;
			#mbox-cells = <0x1>;
			phandle = <0x17>;
		};

		clock-controller@300000 {
			compatible = "qcom,gcc-msm8996";
			#clock-cells = <0x1>;
			#reset-cells = <0x1>;
			#power-domain-cells = <0x1>;
			reg = <0x300000 0x90000>;
			clocks = <0x10 0x4a>;
			clock-names = "cxo2";
			phandle = <0x1b>;
		};

		stm@3002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x3002000 0x1000 0x8280000 0x180000>;
			reg-names = "stm-base", "stm-stimulus-base";
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x1c>;
						phandle = <0x1e>;
					};
				};
			};
		};

		tpiu@3020000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x3020000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x1d>;
						phandle = <0x29>;
					};
				};
			};
		};

		funnel@3021000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3021000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@7 {
					reg = <0x7>;

					endpoint {
						remote-endpoint = <0x1e>;
						phandle = <0x1c>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x1f>;
						phandle = <0x23>;
					};
				};
			};
		};

		funnel@3022000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3022000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@6 {
					reg = <0x6>;

					endpoint {
						remote-endpoint = <0x20>;
						phandle = <0x39>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x21>;
						phandle = <0x24>;
					};
				};
			};
		};

		funnel@3023000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3023000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x22>;
						phandle = <0x25>;
					};
				};
			};
		};

		funnel@3025000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3025000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x23>;
						phandle = <0x1f>;
					};
				};

				port@1 {
					reg = <0x1>;

					endpoint {
						remote-endpoint = <0x24>;
						phandle = <0x21>;
					};
				};

				port@2 {
					reg = <0x2>;

					endpoint {
						remote-endpoint = <0x25>;
						phandle = <0x22>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x26>;
						phandle = <0x2a>;
					};
				};
			};
		};

		replicator@3026000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x3026000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x27>;
						phandle = <0x2b>;
					};
				};
			};

			out-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x28>;
						phandle = <0x2c>;
					};
				};

				port@1 {
					reg = <0x1>;

					endpoint {
						remote-endpoint = <0x29>;
						phandle = <0x1d>;
					};
				};
			};
		};

		etf@3027000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x3027000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x2a>;
						phandle = <0x26>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x2b>;
						phandle = <0x27>;
					};
				};
			};
		};

		etr@3028000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x3028000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";
			arm,scatter-gather;

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x2c>;
						phandle = <0x28>;
					};
				};
			};
		};

		debug@3810000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3810000 0x1000>;
			clocks = <0x10 0x8>;
			clock-names = "apb_pclk";
			cpu = <0x8>;
		};

		etm@3840000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3840000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";
			cpu = <0x8>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x2d>;
						phandle = <0x2f>;
					};
				};
			};
		};

		debug@3910000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3910000 0x1000>;
			clocks = <0x10 0x8>;
			clock-names = "apb_pclk";
			cpu = <0x9>;
		};

		etm@3940000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3940000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";
			cpu = <0x9>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x2e>;
						phandle = <0x30>;
					};
				};
			};
		};

		funnel@39b0000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x39b0000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x2f>;
						phandle = <0x2d>;
					};
				};

				port@1 {
					reg = <0x1>;

					endpoint {
						remote-endpoint = <0x30>;
						phandle = <0x2e>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x31>;
						phandle = <0x37>;
					};
				};
			};
		};

		debug@3a10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3a10000 0x1000>;
			clocks = <0x10 0x8>;
			clock-names = "apb_pclk";
			cpu = <0xa>;
		};

		etm@3a40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3a40000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";
			cpu = <0xa>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x32>;
						phandle = <0x34>;
					};
				};
			};
		};

		debug@3b10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3b10000 0x1000>;
			clocks = <0x10 0x8>;
			clock-names = "apb_pclk";
			cpu = <0xb>;
		};

		etm@3b40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3b40000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";
			cpu = <0xb>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x33>;
						phandle = <0x35>;
					};
				};
			};
		};

		funnel@3bb0000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3bb0000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x34>;
						phandle = <0x32>;
					};
				};

				port@1 {
					reg = <0x1>;

					endpoint {
						remote-endpoint = <0x35>;
						phandle = <0x33>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x36>;
						phandle = <0x38>;
					};
				};
			};
		};

		funnel@3bc0000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3bc0000 0x1000>;
			clocks = <0x10 0x8 0x10 0x9>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x37>;
						phandle = <0x31>;
					};
				};

				port@1 {
					reg = <0x1>;

					endpoint {
						remote-endpoint = <0x38>;
						phandle = <0x36>;
					};
				};
			};

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x39>;
						phandle = <0x20>;
					};
				};
			};
		};

		clock-controller@6400000 {
			compatible = "qcom,apcc-msm8996";
			reg = <0x6400000 0x90000>;
			#clock-cells = <0x1>;
		};

		serial@7570000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x7570000 0x1000>;
			interrupts = <0x0 0x6c 0x4>;
			clocks = <0x1b 0x74 0x1b 0x6d>;
			clock-names = "core", "iface";
			status = "okay";
			label = "BT-UART";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x3a>;
			pinctrl-1 = <0x3b>;

			bluetooth {
				compatible = "qcom,qca6174-bt";
				enable-gpios = <0x11 0x13 0x0>;
				clocks = <0x3c>;
			};
		};

		spi@7575000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x7575000 0x600>;
			interrupts = <0x0 0x5f 0x4>;
			clocks = <0x1b 0x6f 0x1b 0x6d>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x3d>;
			pinctrl-1 = <0x3e>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
		};

		i2c@75b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x75b5000 0x1000>;
			interrupts = <0x0 0x65 0x4>;
			clocks = <0x1b 0x81 0x1b 0x84>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x3f>;
			pinctrl-1 = <0x40>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
		};

		serial@75b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x75b0000 0x1000>;
			interrupts = <0x0 0x72 0x4>;
			clocks = <0x1b 0x88 0x1b 0x81>;
			clock-names = "core", "iface";
			status = "okay";
			label = "LS-UART1";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x41>;
			pinctrl-1 = <0x42>;
		};

		i2c@75b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x75b6000 0x1000>;
			interrupts = <0x0 0x66 0x4>;
			clocks = <0x1b 0x81 0x1b 0x87>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x43>;
			pinctrl-1 = <0x44>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
		};

		serial@75b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x75b1000 0x1000>;
			interrupts = <0x0 0x73 0x4>;
			clocks = <0x1b 0x8b 0x1b 0x81>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		i2c@7577000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x7577000 0x1000>;
			interrupts = <0x0 0x61 0x4>;
			clocks = <0x1b 0x6d 0x1b 0x76>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x45>;
			pinctrl-1 = <0x46>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
		};

		spi@75ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x75ba000 0x600>;
			interrupts = <0x0 0x6a 0x4>;
			clocks = <0x1b 0x92 0x1b 0x81>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x47>;
			pinctrl-1 = <0x48>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
		};

		sdhci@74a4900 {
			status = "okay";
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x74a4900 0x314 0x74a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0x0 0x7d 0x4 0x0 0xdd 0x4>;
			interrupt-names = "hc_irq", "pwr_irq";
			clock-names = "iface", "core", "xo";
			clocks = <0x1b 0x68 0x1b 0x67 0x49>;
			bus-width = <0x4>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>;
			pinctrl-1 = <0x4e 0x4f 0x50 0x51>;
			cd-gpios = <0x52 0x5f 0x1>;
			vmmc-supply = <0x53>;
			vqmmc-supply = <0x54>;
		};

		pinctrl@1010000 {
			compatible = "qcom,msm8996-pinctrl";
			reg = <0x1010000 0x300000>;
			interrupts = <0x0 0xd0 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x52>;

			wcd9xxx_intr {

				wcd_intr_default {
					phandle = <0x83>;

					mux {
						pins = "gpio54";
						function = "gpio";
					};

					config {
						pins = "gpio54";
						drive-strength = <0x2>;
						bias-pull-down;
						input-enable;
					};
				};
			};

			cdc_reset_ctrl {

				cdc_reset_sleep {

					mux {
						pins = "gpio64";
						function = "gpio";
					};

					config {
						pins = "gpio64";
						drive-strength = <0x10>;
						bias-disable;
						output-low;
					};
				};

				cdc_reset_active {
					phandle = <0x82>;

					mux {
						pins = "gpio64";
						function = "gpio";
					};

					config {
						pins = "gpio64";
						drive-strength = <0x10>;
						bias-pull-down;
						output-high;
					};
				};
			};

			blsp1_spi0_default {
				phandle = <0x3d>;

				pinmux {
					function = "blsp_spi1";
					pins = "gpio0", "gpio1", "gpio3";
				};

				pinmux_cs {
					function = "gpio";
					pins = "gpio2";
				};

				pinconf {
					pins = "gpio0", "gpio1", "gpio3";
					drive-strength = <0xc>;
					bias-disable;
				};

				pinconf_cs {
					pins = "gpio2";
					drive-strength = <0x10>;
					bias-disable;
					output-high;
				};
			};

			blsp1_spi0_sleep {
				phandle = <0x3e>;

				pinmux {
					function = "gpio";
					pins = "gpio0", "gpio1", "gpio2", "gpio3";
				};

				pinconf {
					pins = "gpio0", "gpio1", "gpio2", "gpio3";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			blsp1_i2c2_default {
				phandle = <0x45>;

				pinmux {
					function = "blsp_i2c3";
					pins = "gpio47", "gpio48";
				};

				pinconf {
					pins = "gpio47", "gpio48";
					drive-strength = <0x10>;
					bias-disable = <0x0>;
				};
			};

			blsp1_i2c2_sleep {
				phandle = <0x46>;

				pinmux {
					function = "gpio";
					pins = "gpio47", "gpio48";
				};

				pinconf {
					pins = "gpio47", "gpio48";
					drive-strength = <0x2>;
					bias-disable = <0x0>;
				};
			};

			blsp2_i2c0 {
				phandle = <0x3f>;

				pinmux {
					function = "blsp_i2c7";
					pins = "gpio55", "gpio56";
				};

				pinconf {
					pins = "gpio55", "gpio56";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_i2c0_sleep {
				phandle = <0x40>;

				pinmux {
					function = "gpio";
					pins = "gpio55", "gpio56";
				};

				pinconf {
					pins = "gpio55", "gpio56";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_uart1_2pins {
				phandle = <0x41>;

				pinmux {
					function = "blsp_uart8";
					pins = "gpio4", "gpio5";
				};

				pinconf {
					pins = "gpio4", "gpio5";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_uart1_2pins_sleep {
				phandle = <0x42>;

				pinmux {
					function = "gpio";
					pins = "gpio4", "gpio5";
				};

				pinconf {
					pins = "gpio4", "gpio5";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_uart1_4pins {

				pinmux {
					function = "blsp_uart8";
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
				};

				pinconf {
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_uart1_4pins_sleep {

				pinmux {
					function = "gpio";
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
				};

				pinconf {
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_i2c1 {
				phandle = <0x43>;

				pinmux {
					function = "blsp_i2c8";
					pins = "gpio6", "gpio7";
				};

				pinconf {
					pins = "gpio6", "gpio7";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_i2c1_sleep {
				phandle = <0x44>;

				pinmux {
					function = "gpio";
					pins = "gpio6", "gpio7";
				};

				pinconf {
					pins = "gpio6", "gpio7";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_uart2_2pins {

				pinmux {
					function = "blsp_uart9";
					pins = "gpio49", "gpio50";
				};

				pinconf {
					pins = "gpio49", "gpio50";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_uart2_2pins_sleep {

				pinmux {
					function = "gpio";
					pins = "gpio49", "gpio50";
				};

				pinconf {
					pins = "gpio49", "gpio50";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_uart2_4pins {

				pinmux {
					function = "blsp_uart9";
					pins = "gpio49", "gpio50", "gpio51", "gpio52";
				};

				pinconf {
					pins = "gpio49", "gpio50", "gpio51", "gpio52";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp2_uart2_4pins_sleep {

				pinmux {
					function = "gpio";
					pins = "gpio49", "gpio50", "gpio51", "gpio52";
				};

				pinconf {
					pins = "gpio49", "gpio50", "gpio51", "gpio52";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp2_spi5_default {
				phandle = <0x47>;

				pinmux {
					function = "blsp_spi12";
					pins = "gpio85", "gpio86", "gpio88";
				};

				pinmux_cs {
					function = "gpio";
					pins = "gpio87";
				};

				pinconf {
					pins = "gpio85", "gpio86", "gpio88";
					drive-strength = <0xc>;
					bias-disable;
				};

				pinconf_cs {
					pins = "gpio87";
					drive-strength = <0x10>;
					bias-disable;
					output-high;
				};
			};

			blsp2_spi5_sleep {
				phandle = <0x48>;

				pinmux {
					function = "gpio";
					pins = "gpio85", "gpio86", "gpio87", "gpio88";
				};

				pinconf {
					pins = "gpio85", "gpio86", "gpio87", "gpio88";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			sdc2_clk_on {
				phandle = <0x4a>;

				config {
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <0x10>;
				};
			};

			sdc2_clk_off {
				phandle = <0x4e>;

				config {
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <0x2>;
				};
			};

			sdc2_cmd_on {
				phandle = <0x4b>;

				config {
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <0xa>;
				};
			};

			sdc2_cmd_off {
				phandle = <0x4f>;

				config {
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <0x2>;
				};
			};

			sdc2_data_on {
				phandle = <0x4c>;

				config {
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <0xa>;
				};
			};

			sdc2_data_off {
				phandle = <0x50>;

				config {
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <0x2>;
				};
			};

			pcie0_clkreq_default {
				phandle = <0x6f>;

				mux {
					pins = "gpio36";
					function = "pci_e0";
				};

				config {
					pins = "gpio36";
					drive-strength = <0x2>;
					bias-pull-up;
				};
			};

			pcie0_perst_default {
				phandle = <0x70>;

				mux {
					pins = "gpio35";
					function = "gpio";
				};

				config {
					pins = "gpio35";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			pcie0_wake_default {
				phandle = <0x71>;

				mux {
					pins = "gpio37";
					function = "gpio";
				};

				config {
					pins = "gpio37";
					drive-strength = <0x2>;
					bias-pull-up;
				};
			};

			pcie0_clkreq_sleep {
				phandle = <0x72>;

				mux {
					pins = "gpio36";
					function = "gpio";
				};

				config {
					pins = "gpio36";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			pcie0_wake_sleep {
				phandle = <0x73>;

				mux {
					pins = "gpio37";
					function = "gpio";
				};

				config {
					pins = "gpio37";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			pcie1_clkreq_default {
				phandle = <0x75>;

				mux {
					pins = "gpio131";
					function = "pci_e1";
				};

				config {
					pins = "gpio131";
					drive-strength = <0x2>;
					bias-pull-up;
				};
			};

			pcie1_perst_default {
				phandle = <0x76>;

				mux {
					pins = "gpio130";
					function = "gpio";
				};

				config {
					pins = "gpio130";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			pcie1_wake_default {
				phandle = <0x77>;

				mux {
					pins = "gpio132";
					function = "gpio";
				};

				config {
					pins = "gpio132";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			pcie1_clkreq_sleep {
				phandle = <0x78>;

				mux {
					pins = "gpio131";
					function = "gpio";
				};

				config {
					pins = "gpio131";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			pcie1_wake_sleep {
				phandle = <0x79>;

				mux {
					pins = "gpio132";
					function = "gpio";
				};

				config {
					pins = "gpio132";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			pcie2_clkreq_default {
				phandle = <0x7b>;

				mux {
					pins = "gpio115";
					function = "pci_e2";
				};

				config {
					pins = "gpio115";
					drive-strength = <0x2>;
					bias-pull-up;
				};
			};

			pcie2_perst_default {
				phandle = <0x7c>;

				mux {
					pins = "gpio114";
					function = "gpio";
				};

				config {
					pins = "gpio114";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			pcie2_wake_default {
				phandle = <0x7d>;

				mux {
					pins = "gpio116";
					function = "gpio";
				};

				config {
					pins = "gpio116";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			pcie2_clkreq_sleep {
				phandle = <0x7e>;

				mux {
					pins = "gpio115";
					function = "gpio";
				};

				config {
					pins = "gpio115";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			pcie2_wake_sleep {
				phandle = <0x7f>;

				mux {
					pins = "gpio116";
					function = "gpio";
				};

				config {
					pins = "gpio116";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			cci0_default {

				pinmux {
					function = "cci_i2c";
					pins = "gpio17", "gpio18";
				};

				pinconf {
					pins = "gpio17", "gpio18";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			cci1_default {

				pinmux {
					function = "cci_i2c";
					pins = "gpio19", "gpio20";
				};

				pinconf {
					pins = "gpio19", "gpio20";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			camera_board_default {

				mux_pwdn {
					function = "gpio";
					pins = "gpio98";
				};

				config_pwdn {
					pins = "gpio98";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_rst {
					function = "gpio";
					pins = "gpio104";
				};

				config_rst {
					pins = "gpio104";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_mclk1 {
					function = "cam_mclk";
					pins = "gpio14";
				};

				config_mclk1 {
					pins = "gpio14";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			camera_front_default {

				mux_pwdn {
					function = "gpio";
					pins = "gpio133";
				};

				config_pwdn {
					pins = "gpio133";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_rst {
					function = "gpio";
					pins = "gpio23";
				};

				config_rst {
					pins = "gpio23";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_mclk2 {
					function = "cam_mclk";
					pins = "gpio15";
				};

				config_mclk2 {
					pins = "gpio15";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			camera_rear_default {

				mux_pwdn {
					function = "gpio";
					pins = "gpio26";
				};

				config_pwdn {
					pins = "gpio26";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_rst {
					function = "gpio";
					pins = "gpio25";
				};

				config_rst {
					pins = "gpio25";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_mclk0 {
					function = "cam_mclk";
					pins = "gpio13";
				};

				config_mclk0 {
					pins = "gpio13";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			sdc2_cd_on {
				phandle = <0x4d>;

				mux {
					pins = "gpio95";
					function = "gpio";
				};

				config {
					pins = "gpio95";
					bias-pull-up;
					drive-strength = <0x10>;
				};
			};

			sdc2_cd_off {
				phandle = <0x51>;

				mux {
					pins = "gpio95";
					function = "gpio";
				};

				config {
					pins = "gpio95";
					bias-pull-up;
					drive-strength = <0x2>;
				};
			};

			hdmi_hpd_active {
				phandle = <0x8f>;

				mux {
					pins = "gpio34";
					function = "hdmi_hot";
				};

				config {
					pins = "gpio34";
					bias-pull-down;
					drive-strength = <0x10>;
				};
			};

			hdmi_hpd_suspend {
				phandle = <0x91>;

				mux {
					pins = "gpio34";
					function = "hdmi_hot";
				};

				config {
					pins = "gpio34";
					bias-pull-down;
					drive-strength = <0x2>;
				};
			};

			hdmi_ddc_active {
				phandle = <0x90>;

				mux {
					pins = "gpio32", "gpio33";
					function = "hdmi_ddc";
				};

				config {
					pins = "gpio32", "gpio33";
					drive-strength = <0x2>;
					bias-pull-up;
				};
			};

			hdmi_ddc_suspend {
				phandle = <0x92>;

				mux {
					pins = "gpio32", "gpio33";
					function = "hdmi_ddc";
				};

				config {
					pins = "gpio32", "gpio33";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			blsp1_uart1_default {
				phandle = <0x3a>;

				mux {
					pins = "gpio41", "gpio42", "gpio43", "gpio44";
					function = "blsp_uart2";
				};

				config {
					pins = "gpio41", "gpio42", "gpio43", "gpio44";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp1_uart1_sleep {
				phandle = <0x3b>;

				mux {
					pins = "gpio41", "gpio42", "gpio43", "gpio44";
					function = "gpio";
				};

				config {
					pins = "gpio41", "gpio42", "gpio43", "gpio44";
					drive-strength = <0x2>;
					bias-disable;
				};
			};

			blsp12_i2c_default {
				phandle = <0x9d>;

				pinmux {
					function = "blsp_i2c12";
					pins = "gpio87", "gpio88";
				};

				pinconf {
					pins = "gpio87", "gpio88";
					drive-strength = <0x10>;
					bias-disable;
				};
			};

			blsp12_i2c_sleep {
				phandle = <0x9e>;

				pinmux {
					function = "gpio";
					pins = "gpio87", "gpio88";
				};

				pinconf {
					pins = "gpio87", "gpio88";
					drive-strength = <0x2>;
					bias-pull-down;
				};
			};

			camera_primary_default {
				phandle = <0xa0>;

				mux_rst {
					function = "gpio";
					pins = "gpio135";
				};

				config_rst {
					pins = "gpio135";
					drive-strength = <0x10>;
					bias-disable;
				};

				mux_mclk0 {
					function = "cam_mclk";
					pins = "gpio13";
				};

				config_mclk0 {
					pins = "gpio13";
					drive-strength = <0x10>;
					bias-disable;
				};
			};
		};

		timer@9840000 {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x9840000 0x1000>;
			clock-frequency = <0x124f800>;

			frame@9850000 {
				frame-number = <0x0>;
				interrupts = <0x0 0x1f 0x4 0x0 0x1e 0x4>;
				reg = <0x9850000 0x1000 0x9860000 0x1000>;
			};

			frame@9870000 {
				frame-number = <0x1>;
				interrupts = <0x0 0x20 0x4>;
				reg = <0x9870000 0x1000>;
				status = "disabled";
			};

			frame@9880000 {
				frame-number = <0x2>;
				interrupts = <0x0 0x21 0x4>;
				reg = <0x9880000 0x1000>;
				status = "disabled";
			};

			frame@9890000 {
				frame-number = <0x3>;
				interrupts = <0x0 0x22 0x4>;
				reg = <0x9890000 0x1000>;
				status = "disabled";
			};

			frame@98a0000 {
				frame-number = <0x4>;
				interrupts = <0x0 0x23 0x4>;
				reg = <0x98a0000 0x1000>;
				status = "disabled";
			};

			frame@98b0000 {
				frame-number = <0x5>;
				interrupts = <0x0 0x24 0x4>;
				reg = <0x98b0000 0x1000>;
				status = "disabled";
			};

			frame@98c0000 {
				frame-number = <0x6>;
				interrupts = <0x0 0x25 0x4>;
				reg = <0x98c0000 0x1000>;
				status = "disabled";
			};
		};

		qcom,spmi@400f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x400f000 0x1000 0x4400000 0x800000 0x4c00000 0x800000 0x5800000 0x200000 0x400a000 0x2100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <0x0 0x146 0x4>;
			qcom,ee = <0x0>;
			qcom,channel = <0x0>;
			#address-cells = <0x2>;
			#size-cells = <0x0>;
			interrupt-controller;
			#interrupt-cells = <0x4>;

			pmic@0 {
				compatible = "qcom,pm8994", "qcom,spmi-pmic";
				reg = <0x0 0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				rtc@6000 {
					compatible = "qcom,pm8941-rtc";
					reg = <0x6000 0x6100>;
					reg-names = "rtc", "alarm";
					interrupts = <0x0 0x61 0x1 0x1>;
				};

				pon@800 {
					compatible = "qcom,pm8916-pon";
					reg = <0x800>;
					mode-bootloader = <0x2>;
					mode-recovery = <0x1>;

					pwrkey {
						compatible = "qcom,pm8941-pwrkey";
						interrupts = <0x0 0x8 0x0 0x3>;
						debounce = <0x3d09>;
						bias-pull-up;
						linux,code = <0x74>;
					};

					resin {
						compatible = "qcom,pm8941-resin";
						interrupts = <0x0 0x8 0x1 0x3>;
						debounce = <0x3d09>;
						bias-pull-up;
						linux,code = <0x72>;
					};
				};

				pmic_vadc@3100 {
					compatible = "qcom,spmi-vadc";
					reg = <0x3100>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#io-channel-cells = <0x1>;

					blsp_exp_ain1 {
						reg = <0x35>;
					};

					vadc_ref_1250mv {
						reg = <0xa>;
					};

					vadc_ref_625mv {
						reg = <0x9>;
					};

					vadc_gnd_ref {
						reg = <0xe>;
					};

					vadc_vdd_vadc {
						reg = <0xf>;
					};
				};

				gpios@c000 {
					compatible = "qcom,pm8994-gpio";
					reg = <0xc000>;
					gpio-controller;
					#gpio-cells = <0x2>;
					interrupts = <0x0 0xc0 0x0 0x0 0x0 0xc1 0x0 0x0 0x0 0xc2 0x0 0x0 0x0 0xc3 0x0 0x0 0x0 0xc4 0x0 0x0 0x0 0xc5 0x0 0x0 0x0 0xc6 0x0 0x0 0x0 0xc7 0x0 0x0 0x0 0xc8 0x0 0x0 0x0 0xc9 0x0 0x0 0x0 0xca 0x0 0x0 0x0 0xcb 0x0 0x0 0x0 0xcc 0x0 0x0 0x0 0xcd 0x0 0x0 0x0 0xce 0x0 0x0 0x0 0xcf 0x0 0x0 0x0 0xd0 0x0 0x0 0x0 0xd1 0x0 0x0 0x0 0xd2 0x0 0x0 0x0 0xd3 0x0 0x0 0x0 0xd4 0x0 0x0 0x0 0xd5 0x0 0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0x55 0x56>;
					phandle = <0x11>;

					pm8994_gpio5 {
						phandle = <0x55>;

						pinconf {
							pins = "gpio5";
							function = "normal";
							output-high;
							power-source = <0x2>;
							qcom,drive-strength = <0x3>;
							bias-pull-down;
						};
					};

					bt_en_gpios {
						phandle = <0x56>;

						pinconf {
							pins = "gpio19";
							function = "normal";
							output-low;
							power-source = <0x2>;
							qcom,drive-strength = <0x3>;
							bias-pull-down;
						};
					};

					wlan_en_gpios {
						phandle = <0x9c>;

						pinconf {
							pins = "gpio8";
							function = "normal";
							output-low;
							power-source = <0x2>;
							qcom,drive-strength = <0x3>;
							bias-pull-down;
						};
					};

					clk_div1 {
						phandle = <0xf>;

						pinconf {
							pins = "gpio15";
							function = "func1";
							power-source = <0x2>;
						};
					};

					pm8996_gpio2 {

						pinconf {
							pins = "gpio2";
							function = "normal";
							input-enable;
							drive-push-pull;
							bias-pull-up;
							qcom,drive-strength = <0x0>;
							power-source = <0x2>;
						};
					};

					divclk4 {
						phandle = <0xe>;

						pinconf {
							pins = "gpio18";
							function = "func2";
							bias-disable;
							power-source = <0x2>;
						};
					};

					pmi8996_gpio22 {
						phandle = <0xa5>;

						pinconf {
							pins = "gpio22";
							function = "normal";
							input-enable;
							bias-pull-down;
							qcom,drive-strength = <0x0>;
							power-source = <0x2>;
						};
					};
				};

				mpps@a000 {
					compatible = "qcom,pm8994-mpp";
					reg = <0xa000>;
					gpio-controller;
					#gpio-cells = <0x2>;
					interrupts = <0x0 0xa0 0x0 0x0 0x0 0xa1 0x0 0x0 0x0 0xa2 0x0 0x0 0x0 0xa3 0x0 0x0 0x0 0xa4 0x0 0x0 0x0 0xa5 0x0 0x0 0x0 0xa6 0x0 0x0 0x0 0xa7 0x0 0x0>;

					mpp2-wifi-led-active {
						pins = "mpp2";
						function = "sink";
						output-low;
						qcom,dtest = <0x1>;
						phandle = <0x57>;
					};

					mpp4-wifi-led-active {
						pins = "mpp4";
						function = "sink";
						output-low;
						qcom,dtest = <0x2>;
						phandle = <0x58>;
					};
				};
			};

			pmic@1 {
				compatible = "qcom,pm8994", "qcom,spmi-pmic";
				reg = <0x1 0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				lpg {
					compatible = "qcom,pm8994-lpg";
					status = "okay";
					qcom,dtest = <0x1 0x2 0x2 0x2 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0x57 0x58>;

					wifi-led {
						led-sources = <0x1>;
						linux,default-trigger = "phy0tx";
						default-state = "off";
					};

					bt-led {
						led-sources = <0x2>;
						linux,default-trigger = "hci0-power";
						default-state = "off";
					};
				};
			};

			pmic@2 {
				compatible = "qcom,pmi8994", "qcom,spmi-pmic";
				reg = <0x2 0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				qcom,power-on@800 {
					compatible = "qcom,qpnp-power-on";
					reg = <0x800 0x100>;
					qcom,secondary-pon-reset;

					qcom,pon_perph_reg {
						regulator-name = "pon_spare_reg";
						qcom,pon-spare-reg-addr = <0x8c>;
						qcom,pon-spare-reg-bit = <0x1>;
						phandle = <0x5b>;
					};
				};

				gpios@c000 {
					compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
					reg = <0xc000>;
					gpio-controller;
					gpio-ranges = <0x59 0x0 0x0 0xa>;
					#gpio-cells = <0x2>;
					interrupt-controller;
					#interrupt-cells = <0x2>;
					interrupts = <0x2 0xc0 0x0 0x0 0x2 0xc1 0x0 0x0 0x2 0xc2 0x0 0x0 0x2 0xc3 0x0 0x0 0x2 0xc4 0x0 0x0 0x2 0xc5 0x0 0x0 0x2 0xc6 0x0 0x0 0x2 0xc7 0x0 0x0 0x2 0xc8 0x0 0x0 0x2 0xc9 0x0 0x0>;
					phandle = <0x59>;

					pmi8996_gpio6 {

						pinconf {
							pins = "gpio6";
							function = "normal";
							input-enable;
							bias-pull-down;
							qcom,drive-strength = <0x0>;
							power-source = <0x2>;
						};
					};
				};

				mpps@a000 {
					compatible = "qcom,pm8994-mpp";
					reg = <0xa000>;
					gpio-controller;
					#gpio-cells = <0x2>;
					interrupts = <0x0 0xa0 0x0 0x0 0x0 0xa1 0x0 0x0 0x0 0xa2 0x0 0x0 0x0 0xa3 0x0 0x0>;

					mpp2-userled4 {
						pins = "mpp2";
						function = "sink";
						output-low;
						qcom,dtest = <0x4>;
						phandle = <0x5a>;
					};
				};
			};

			pmic@3 {
				compatible = "qcom,pmi8994", "qcom,spmi-pmic";
				reg = <0x3 0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				lpg@b100 {
					compatible = "qcom,pmi8994-lpg";
					status = "okay";
					qcom,power-source = <0x1>;
					qcom,dtest = <0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x1>;
					pinctrl-names = "default";
					pinctrl-0 = <0x5a>;

					user0 {
						led-sources = <0x2>;
						label = "db820c:green:user0";
						default-state = "on";
						linux,default-trigger = "heartbeat";
					};

					user1 {
						led-sources = <0x1>;
						label = "db820c:green:user1";
					};

					user2 {
						led-sources = <0x3>;
						label = "db820c:green:user2";
					};

					user3 {
						led-sources = <0x4>;
						label = "db820c:green:user3";
						qcom,dtest = <0x4 0x1>;
					};
				};

				regulators {
					compatible = "qcom,pmi8994-regulators";
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					s2@1700 {
						reg = <0x1700 0x100>;
						status = "ok";
						regulator-min-microvolt = <0x61a80>;
						regulator-max-microvolt = <0xf7cd8>;
						regulator-always-on;
					};
				};

				qcom,haptic@c000 {
					status = "disabled";
					compatible = "qcom,qpnp-haptic";
					reg = <0xc000 0x100>;
					interrupts = <0x3 0xc0 0x0 0x3 0xc0 0x1>;
					interrupt-names = "sc-irq", "play-irq";
					vcc_pon-supply = <0x5b>;
					qcom,play-mode = "direct";
					qcom,wave-play-rate-us = <0x4a38>;
					qcom,actuator-type = "erm";
					qcom,vmax-mv = <0xbb8>;
					qcom,int-pwm-freq-khz = <0x1f9>;
				};
			};
		};

		phy@627000 {
			compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
			reg = <0x627000 0xda8>;
			reg-names = "phy_mem";
			#phy-cells = <0x0>;
			vdda-phy-supply = <0x5c>;
			vdda-pll-supply = <0x5d>;
			vdda-phy-max-microamp = <0x47cc>;
			vdda-pll-max-microamp = <0x24e0>;
			vddp-ref-clk-supply = <0x5e>;
			vddp-ref-clk-max-microamp = <0x64>;
			vddp-ref-clk-always-on;
			clock-names = "ref_clk_src", "ref_clk";
			clocks = <0x10 0x4a 0x1b 0xd7>;
			resets = <0x5f 0x0>;
			status = "disabled";
			phandle = <0x60>;
		};

		ufshc@624000 {
			compatible = "qcom,ufshc";
			reg = <0x624000 0x2500>;
			interrupts = <0x0 0x109 0x4>;
			phys = <0x60>;
			phy-names = "ufsphy";
			vcc-supply = <0x61>;
			vccq-supply = <0x5e>;
			vccq2-supply = <0x62>;
			vcc-max-microamp = <0x927c0>;
			vccq-max-microamp = <0x6ddd0>;
			vccq2-max-microamp = <0x6ddd0>;
			power-domains = <0x1b 0x8>;
			clock-names = "core_clk_src", "core_clk", "bus_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro_src", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk";
			clocks = <0x1b 0x49 0x1b 0xc1 0x1b 0x52 0x1b 0xd1 0x1b 0xc2 0x1b 0x4a 0x1b 0xc8 0x1b 0xc9 0x10 0x4a 0x1b 0xc5 0x1b 0xc6>;
			freq-table-hz = <0x5f5e100 0xbebc200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8f0d180 0x11e1a300 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
			lanes-per-direction = <0x1>;
			#reset-cells = <0x1>;
			status = "okay";
			phandle = <0x5f>;

			ufs_variant {
				compatible = "qcom,ufs_variant";
			};
		};

		clock-controller@8c0000 {
			compatible = "qcom,mmcc-msm8996";
			#clock-cells = <0x1>;
			#reset-cells = <0x1>;
			#power-domain-cells = <0x1>;
			reg = <0x8c0000 0x40000>;
			assigned-clocks = <0x63 0xf 0x63 0x3 0x63 0x7 0x63 0x9 0x63 0xb>;
			assigned-clock-rates = <0x25317c00 0x30479e80 0x3a699d00 0x39387000 0x312c8040>;
			phandle = <0x63>;
		};

		qfprom@74000 {
			compatible = "qcom,qfprom";
			reg = <0x74000 0x8ff>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			hstx_trim@24e {
				reg = <0x24e 0x2>;
				bits = <0x5 0x4>;
				phandle = <0x65>;
			};

			hstx_trim@24f {
				reg = <0x24f 0x1>;
				bits = <0x1 0x4>;
				phandle = <0x66>;
			};

			gpu_speed_bin@133 {
				reg = <0x133 0x1>;
				bits = <0x5 0x3>;
				phandle = <0x87>;
			};
		};

		phy@34000 {
			compatible = "qcom,msm8996-qmp-pcie-phy";
			reg = <0x34000 0x488>;
			#clock-cells = <0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			clocks = <0x1b 0xc0 0x1b 0xbf 0x1b 0xd8>;
			clock-names = "aux", "cfg_ahb", "ref";
			vdda-phy-supply = <0x5c>;
			vdda-pll-supply = <0x5d>;
			resets = <0x1b 0x55 0x1b 0x65 0x1b 0x66>;
			reset-names = "phy", "common", "cfg";
			status = "okay";

			lane@35000 {
				reg = <0x35000 0x130 0x35200 0x200 0x35400 0x1dc>;
				#phy-cells = <0x0>;
				clock-output-names = "pcie_0_pipe_clk_src";
				clocks = <0x1b 0xb4>;
				clock-names = "pipe0";
				resets = <0x1b 0x50>;
				reset-names = "lane0";
				phandle = <0x6e>;
			};

			lane@36000 {
				reg = <0x36000 0x130 0x36200 0x200 0x36400 0x1dc>;
				#phy-cells = <0x0>;
				clock-output-names = "pcie_1_pipe_clk_src";
				clocks = <0x1b 0xb9>;
				clock-names = "pipe1";
				resets = <0x1b 0x52>;
				reset-names = "lane1";
				phandle = <0x74>;
			};

			lane@37000 {
				reg = <0x37000 0x130 0x37200 0x200 0x37400 0x1dc>;
				#phy-cells = <0x0>;
				clock-output-names = "pcie_2_pipe_clk_src";
				clocks = <0x1b 0xbe>;
				clock-names = "pipe2";
				resets = <0x1b 0x54>;
				reset-names = "lane2";
				phandle = <0x7a>;
			};
		};

		phy@7410000 {
			compatible = "qcom,msm8996-qmp-usb3-phy";
			reg = <0x7410000 0x1c4>;
			#clock-cells = <0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			clocks = <0x1b 0x5e 0x1b 0x63 0x1b 0xd5>;
			clock-names = "aux", "cfg_ahb", "ref";
			vdda-phy-supply = <0x5c>;
			vdda-pll-supply = <0x5d>;
			resets = <0x1b 0x67 0x1b 0x68>;
			reset-names = "phy", "common";
			status = "okay";

			lane@7410200 {
				reg = <0x7410200 0x200 0x7410400 0x130 0x7410600 0x1a8>;
				#phy-cells = <0x0>;
				clock-output-names = "usb3_phy_pipe_clk_src";
				clocks = <0x1b 0x5f>;
				clock-names = "pipe0";
				phandle = <0x6a>;
			};
		};

		phy@7411000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x7411000 0x180>;
			#phy-cells = <0x0>;
			clocks = <0x1b 0x63 0x1b 0xda>;
			clock-names = "cfg_ahb", "ref";
			vdda-pll-supply = <0x5d>;
			vdda-phy-dpdm-supply = <0x64>;
			resets = <0x1b 0x9>;
			nvmem-cells = <0x65>;
			status = "okay";
			phandle = <0x69>;
		};

		phy@7412000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x7412000 0x180>;
			#phy-cells = <0x0>;
			clocks = <0x1b 0x63 0x1b 0xd9>;
			clock-names = "cfg_ahb", "ref";
			vdda-pll-supply = <0x5d>;
			vdda-phy-dpdm-supply = <0x64>;
			resets = <0x1b 0xa>;
			nvmem-cells = <0x66>;
			status = "okay";
			phandle = <0x67>;
		};

		usb@76f8800 {
			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
			reg = <0x76f8800 0x400>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			clocks = <0x1b 0x55 0x1b 0x60 0x1b 0x62 0x1b 0x61 0x1b 0x63>;
			assigned-clocks = <0x1b 0x62 0x1b 0x60>;
			assigned-clock-rates = <0x124f800 0x3938700>;
			power-domains = <0x1b 0x4>;
			status = "okay";

			dwc3@7600000 {
				compatible = "snps,dwc3";
				reg = <0x7600000 0xcc00>;
				interrupts = <0x0 0x8a 0x4>;
				phys = <0x67>;
				phy-names = "usb2-phy";
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				dr_mode = "host";
				maximum-speed = "high-speed";
			};
		};

		usb@6af8800 {
			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
			reg = <0x6af8800 0x400>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			clocks = <0x1b 0x51 0x1b 0x5b 0x1b 0xd2 0x1b 0x5d 0x1b 0x5c 0x1b 0x63>;
			assigned-clocks = <0x1b 0x5d 0x1b 0x5b>;
			assigned-clock-rates = <0x124f800 0x7270e00>;
			power-domains = <0x1b 0x4>;
			status = "okay";
			extcon = <0x68>;

			dwc3@6a00000 {
				compatible = "snps,dwc3";
				reg = <0x6a00000 0xcc00>;
				interrupts = <0x0 0x83 0x4>;
				phys = <0x69 0x6a>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				extcon = <0x68>;
				dr_mode = "otg";
				status = "ok";
			};
		};

		iommu@da0000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xda0000 0x10000>;
			#global-interrupts = <0x1>;
			interrupts = <0x0 0x4c 0x4 0x0 0x157 0x4 0x0 0x158 0x4>;
			power-domains = <0x63 0x2>;
			clocks = <0x63 0x4e 0x63 0x4f>;
			clock-names = "iface", "bus";
			#iommu-cells = <0x1>;
			phandle = <0x6c>;
		};

		camss@a00000 {
			compatible = "qcom,msm8996-camss";
			reg = <0xa34000 0x1000 0xa00030 0x4 0xa35000 0x1000 0xa00038 0x4 0xa36000 0x1000 0xa00040 0x4 0xa30000 0x100 0xa30400 0x100 0xa30800 0x100 0xa30c00 0x100 0xa31000 0x500 0xa00020 0x10 0xa10000 0x1000 0xa14000 0x1000>;
			reg-names = "csiphy0", "csiphy0_clk_mux", "csiphy1", "csiphy1_clk_mux", "csiphy2", "csiphy2_clk_mux", "csid0", "csid1", "csid2", "csid3", "ispif", "csi_clk_mux", "vfe0", "vfe1";
			interrupts = <0x0 0x4e 0x0 0x0 0x4f 0x0 0x0 0x50 0x0 0x0 0x128 0x0 0x0 0x129 0x0 0x0 0x12a 0x0 0x0 0x12b 0x0 0x0 0x135 0x0 0x0 0x13a 0x0 0x0 0x13b 0x0>;
			interrupt-names = "csiphy0", "csiphy1", "csiphy2", "csid0", "csid1", "csid2", "csid3", "ispif", "vfe0", "vfe1";
			power-domains = <0x63 0x8>;
			clocks = <0x63 0x81 0x63 0xb9 0x63 0x8c 0x63 0x8d 0x63 0x8e 0x63 0xa6 0x63 0xa5 0x63 0xa7 0x63 0xa9 0x63 0xa8 0x63 0xab 0x63 0xaa 0x63 0xac 0x63 0xae 0x63 0xad 0x63 0xb0 0x63 0xaf 0x63 0xb1 0x63 0xb3 0x63 0xb2 0x63 0xb5 0x63 0xb4 0x63 0xb6 0x63 0xb8 0x63 0xb7 0x63 0x82 0x63 0x99 0x63 0x9f 0x63 0x9b 0x63 0x9a 0x63 0x9c 0x63 0xa0 0x63 0x9e 0x63 0x9d 0x63 0x97 0x63 0x98>;
			clock-names = "top_ahb", "ispif_ahb", "csiphy0_timer", "csiphy1_timer", "csiphy2_timer", "csi0_ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", "csi1_ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", "csi2_ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", "csi3_ahb", "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", "ahb", "vfe0", "csi_vfe0", "vfe0_ahb", "vfe0_stream", "vfe1", "csi_vfe1", "vfe1_ahb", "vfe1_stream", "vfe_ahb", "vfe_axi";
			vdda-supply = <0x6b>;
			iommus = <0x6c 0x0 0x6c 0x1 0x6c 0x2 0x6c 0x3>;
			status = "ok";

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						clock-lanes = <0x7>;
						data-lanes = <0x0 0x1>;
						remote-endpoint = <0x6d>;
						status = "ok";
						phandle = <0xa4>;
					};
				};
			};
		};

		iommu@b40000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xb40000 0x10000>;
			#global-interrupts = <0x1>;
			interrupts = <0x0 0x14e 0x4 0x0 0x149 0x4 0x0 0x14a 0x4>;
			#iommu-cells = <0x1>;
			clocks = <0x63 0x68 0x1b 0x5a>;
			clock-names = "iface", "bus";
			power-domains = <0x63 0x3>;
			phandle = <0x86>;
		};

		iommu@d00000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xd00000 0x10000>;
			#global-interrupts = <0x1>;
			interrupts = <0x0 0x49 0x4 0x0 0x140 0x4 0x0 0x141 0x4>;
			#iommu-cells = <0x1>;
			clocks = <0x63 0x5b 0x63 0x5c>;
			clock-names = "iface", "bus";
			power-domains = <0x63 0xd>;
			phandle = <0x8c>;
		};

		iommu@1600000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0x1600000 0x20000>;
			#iommu-cells = <0x1>;
			power-domains = <0x1b 0x3>;
			#global-interrupts = <0x1>;
			interrupts = <0x0 0x194 0x4 0x0 0xe2 0x4 0x0 0x189 0x4 0x0 0x18a 0x4 0x0 0x18b 0x4 0x0 0x18c 0x4 0x0 0x18d 0x4 0x0 0x18e 0x4 0x0 0x18f 0x4 0x0 0x190 0x4 0x0 0x191 0x4 0x0 0x192 0x4 0x0 0x193 0x4>;
			clocks = <0x1b 0xdb 0x1b 0xdc>;
			clock-names = "iface", "bus";
			phandle = <0xae>;
		};

		agnoc@0 {
			power-domains = <0x1b 0x0>;
			compatible = "simple-pm-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;

			pcie@600000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				status = "disabled";
				power-domains = <0x1b 0x5>;
				bus-range = <0x0 0xff>;
				num-lanes = <0x1>;
				reg = <0x600000 0x2000 0xc000000 0xf1d 0xc000f20 0xa8 0xc100000 0x100000>;
				reg-names = "parf", "dbi", "elbi", "config";
				phys = <0x6e>;
				phy-names = "pciephy";
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				ranges = <0x1000000 0x0 0xc200000 0xc200000 0x0 0x100000 0x2000000 0x0 0xc300000 0xc300000 0x0 0xd00000>;
				interrupts = <0x0 0x195 0x4>;
				interrupt-names = "msi";
				#interrupt-cells = <0x1>;
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xf4 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0xf5 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0xf7 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0xf8 0x4>;
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <0x6f 0x70 0x71>;
				pinctrl-1 = <0x72 0x70 0x73>;
				vdda-supply = <0x5c>;
				linux,pci-domain = <0x0>;
				clocks = <0x1b 0xb4 0x1b 0xb3 0x1b 0xb2 0x1b 0xb1 0x1b 0xb0>;
				clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
			};

			pcie@608000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				power-domains = <0x1b 0x6>;
				bus-range = <0x0 0xff>;
				num-lanes = <0x1>;
				status = "disabled";
				reg = <0x608000 0x2000 0xd000000 0xf1d 0xd000f20 0xa8 0xd100000 0x100000>;
				reg-names = "parf", "dbi", "elbi", "config";
				phys = <0x74>;
				phy-names = "pciephy";
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				ranges = <0x1000000 0x0 0xd200000 0xd200000 0x0 0x100000 0x2000000 0x0 0xd300000 0xd300000 0x0 0xd00000>;
				interrupts = <0x0 0x19d 0x4>;
				interrupt-names = "msi";
				#interrupt-cells = <0x1>;
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x110 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x111 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x112 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x113 0x4>;
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <0x75 0x76 0x77>;
				pinctrl-1 = <0x78 0x76 0x79>;
				vdda-supply = <0x5c>;
				linux,pci-domain = <0x1>;
				clocks = <0x1b 0xb9 0x1b 0xb8 0x1b 0xb7 0x1b 0xb6 0x1b 0xb5>;
				clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
			};

			pcie@610000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				power-domains = <0x1b 0x7>;
				bus-range = <0x0 0xff>;
				num-lanes = <0x1>;
				status = "disabled";
				reg = <0x610000 0x2000 0xe000000 0xf1d 0xe000f20 0xa8 0xe100000 0x100000>;
				reg-names = "parf", "dbi", "elbi", "config";
				phys = <0x7a>;
				phy-names = "pciephy";
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				ranges = <0x1000000 0x0 0xe200000 0xe200000 0x0 0x100000 0x2000000 0x0 0xe300000 0xe300000 0x0 0x1d00000>;
				device_type = "pci";
				interrupts = <0x0 0x1a5 0x4>;
				interrupt-names = "msi";
				#interrupt-cells = <0x1>;
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x8e 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x8f 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x90 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x91 0x4>;
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <0x7b 0x7c 0x7d>;
				pinctrl-1 = <0x7e 0x7c 0x7f>;
				vdda-supply = <0x5c>;
				linux,pci-domain = <0x2>;
				clocks = <0x1b 0xbe 0x1b 0xbd 0x1b 0xbc 0x1b 0xbb 0x1b 0xba>;
				clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
			};

			qcom,pcie@00600000 {
				status = "okay";
				perst-gpio = <0x52 0x23 0x1>;
				vddpe-3v3-supply = <0x80>;
			};

			qcom,pcie@00610000 {
				status = "okay";
				perst-gpio = <0x52 0x72 0x1>;
			};
		};

		dma@9184000 {
			compatible = "qcom,bam-v1.7.0";
			qcom,controlled-remotely;
			reg = <0x9184000 0x32000>;
			num-channels = <0x1f>;
			interrupts = <0x0 0xa4 0x4>;
			#dma-cells = <0x1>;
			qcom,ee = <0x1>;
			qcom,num-ees = <0x2>;
			phandle = <0x81>;
		};

		slim@91c0000 {
			compatible = "qcom,slim-ngd-v1.5.0";
			reg = <0x91c0000 0x2c000>;
			reg-names = "ctrl";
			interrupts = <0x0 0xa3 0x4>;
			dmas = <0x81 0x3 0x81 0x4 0x81 0x5 0x81 0x6>;
			dma-names = "rx", "tx", "tx2", "rx2";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			ngd@1 {
				reg = <0x1>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;

				tas-ifd {
					compatible = "slim217,1a0";
					reg = <0x0 0x0>;
					phandle = <0x84>;
				};

				codec@1 {
					pinctrl-0 = <0x82 0x83>;
					pinctrl-names = "default";
					compatible = "slim217,1a0";
					reg = <0x1 0x0>;
					interrupt-parent = <0x52>;
					interrupts = <0x36 0x4 0x35 0x4>;
					interrupt-names = "intr1", "intr2";
					interrupt-controller;
					#interrupt-cells = <0x1>;
					reset-gpios = <0x52 0x40 0x0>;
					slim-ifc-dev = <0x84>;
					vdd-buck-supply = <0x62>;
					vdd-buck-sido-supply = <0x62>;
					vdd-tx-supply = <0x62>;
					vdd-rx-supply = <0x62>;
					vdd-io-supply = <0x62>;
					#sound-dai-cells = <0x1>;
					clock-names = "mclk", "slimbus";
					clocks = <0x85 0x10 0xa>;
					qcom,mbhc-vthreshold = <0x4b 0x96 0xed 0x1f4 0x1f4 0x1f4 0x1f4 0x1f4>;
					phandle = <0xaa>;
				};
			};
		};

		gpu@b00000 {
			compatible = "qcom,adreno-530.2", "qcom,adreno";
			#stream-id-cells = <0x10>;
			reg = <0xb00000 0x3f000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <0x0 0x12c 0x4>;
			clocks = <0x63 0x66 0x63 0x68 0x63 0x67 0x1b 0xa8 0x1b 0x5a>;
			clock-names = "core", "iface", "rbbmtimer", "mem", "mem_iface";
			power-domains = <0x63 0x3>;
			iommus = <0x86 0x0>;
			nvmem-cells = <0x87>;
			nvmem-cell-names = "speed_bin";
			qcom,gpu-quirk-two-pass-use-wfi;
			qcom,gpu-quirk-fault-detect-mask;
			operating-points-v2 = <0x88>;

			opp-table {
				compatible = "operating-points-v2";
				phandle = <0x88>;

				opp-624000000 {
					opp-hz = <0x0 0x25317c00>;
					opp-supported-hw = <0x1>;
				};

				opp-560000000 {
					opp-hz = <0x0 0x2160ec00>;
					opp-supported-hw = <0x1>;
				};

				opp-510000000 {
					opp-hz = <0x0 0x1e65fb80>;
					opp-supported-hw = <0xff>;
				};

				opp-401800000 {
					opp-hz = <0x0 0x17f2fb40>;
					opp-supported-hw = <0xff>;
				};

				opp-315000000 {
					opp-hz = <0x0 0x12c684c0>;
					opp-supported-hw = <0xff>;
				};

				opp-214000000 {
					opp-hz = <0x0 0xcc16180>;
					opp-supported-hw = <0xff>;
				};

				opp-133000000 {
					opp-hz = <0x0 0x7ed6b40>;
					opp-supported-hw = <0xff>;
				};
			};

			zap-shader {
				memory-region = <0x89>;
			};
		};

		mdss@900000 {
			compatible = "qcom,mdss";
			reg = <0x900000 0x1000 0x9b0000 0x1040 0x9b8000 0x1040>;
			reg-names = "mdss_phys", "vbif_phys", "vbif_nrt_phys";
			power-domains = <0x63 0xd>;
			interrupts = <0x0 0x53 0x4>;
			interrupt-controller;
			#interrupt-cells = <0x1>;
			clocks = <0x63 0x74>;
			clock-names = "iface";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			vdd-supply = <0x8a>;
			status = "okay";
			phandle = <0x8b>;

			mdp@901000 {
				compatible = "qcom,mdp5";
				reg = <0x901000 0x90000>;
				reg-names = "mdp_phys";
				interrupt-parent = <0x8b>;
				interrupts = <0x0 0x4>;
				clocks = <0x63 0x74 0x63 0x76 0x63 0x79 0x63 0x5c 0x63 0x7b>;
				clock-names = "iface", "bus", "core", "iommu", "vsync";
				iommus = <0x8c 0x0>;
				status = "okay";

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;

						endpoint {
							remote-endpoint = <0x8d>;
							phandle = <0x93>;
						};
					};
				};
			};

			hdmi-tx@9a0000 {
				compatible = "qcom,hdmi-tx-8996";
				reg = <0x9a0000 0x50c 0x70000 0x6158 0x9e0000 0xfff>;
				reg-names = "core_physical", "qfprom_physical", "hdcp_physical";
				interrupt-parent = <0x8b>;
				interrupts = <0x8 0x4>;
				clocks = <0x63 0x79 0x63 0x74 0x63 0x7c 0x63 0x75 0x63 0x7a>;
				clock-names = "mdp_core", "iface", "core", "alt_iface", "extp";
				phys = <0x8e>;
				phy-names = "hdmi_phy";
				#sound-dai-cells = <0x1>;
				status = "okay";
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <0x8f 0x90>;
				pinctrl-1 = <0x91 0x92>;
				core-vdda-supply = <0x5d>;
				core-vcc-supply = <0x62>;
				phandle = <0xa9>;

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;

						endpoint {
							remote-endpoint = <0x93>;
							phandle = <0x8d>;
						};
					};
				};
			};

			hdmi-phy@9a0600 {
				#phy-cells = <0x0>;
				compatible = "qcom,hdmi-phy-8996";
				reg = <0x9a0600 0x1c4 0x9a0a00 0x124 0x9a0c00 0x124 0x9a0e00 0x124 0x9a1000 0x124 0x9a1200 0xc8>;
				reg-names = "hdmi_pll", "hdmi_tx_l0", "hdmi_tx_l1", "hdmi_tx_l2", "hdmi_tx_l3", "hdmi_phy";
				clocks = <0x63 0x74 0x1b 0xd6>;
				clock-names = "iface", "ref";
				status = "okay";
				vddio-supply = <0x5d>;
				vcca-supply = <0x5c>;
				phandle = <0x8e>;
			};
		};

		arm,smmu-venus@d40000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xd40000 0x20000>;
			#global-interrupts = <0x1>;
			interrupts = <0x0 0x11e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4 0x0 0x152 0x4 0x0 0x153 0x4 0x0 0x154 0x4 0x0 0x155 0x4>;
			power-domains = <0x63 0x0>;
			clocks = <0x63 0x62 0x63 0x63>;
			clock-names = "iface", "bus";
			#iommu-cells = <0x1>;
			status = "okay";
			phandle = <0x94>;
		};

		video-codec@c00000 {
			compatible = "qcom,msm8996-venus";
			reg = <0xc00000 0xff000>;
			interrupts = <0x0 0x11f 0x4>;
			power-domains = <0x63 0x4>;
			clocks = <0x63 0x6e 0x63 0x71 0x63 0x6f 0x63 0x70>;
			clock-names = "core", "iface", "bus", "mbus";
			iommus = <0x94 0x0 0x94 0x1 0x94 0xa 0x94 0x7 0x94 0xe 0x94 0xf 0x94 0x8 0x94 0x9 0x94 0xb 0x94 0xc 0x94 0xd 0x94 0x10 0x94 0x11 0x94 0x21 0x94 0x28 0x94 0x29 0x94 0x2b 0x94 0x2c 0x94 0x2d 0x94 0x31>;
			memory-region = <0x95>;
			status = "okay";

			video-decoder {
				compatible = "venus-decoder";
				clocks = <0x63 0x72>;
				clock-names = "core";
				power-domains = <0x63 0x5>;
			};

			video-encoder {
				compatible = "venus-encoder";
				clocks = <0x63 0x73>;
				clock-names = "core";
				power-domains = <0x63 0x6>;
			};
		};

		remoteproc@2080000 {
			compatible = "qcom,msm8996-mss-pil";
			reg = <0x2080000 0x100 0x2180000 0x40>;
			reg-names = "qdsp6", "rmb";
			interrupts-extended = <0x1 0x0 0x1c0 0x1 0x96 0x0 0x1 0x96 0x1 0x1 0x96 0x2 0x1 0x96 0x3 0x1>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
			clocks = <0x49 0x1b 0xde 0x10 0x2 0x1b 0xdf 0x1b 0x9d 0x1b 0xe5 0x1b 0xe0 0x1b 0xe1 0x10 0x8>;
			clock-names = "xo", "iface", "pnoc", "bus", "mem", "gpll0_mss", "snoc_axi", "mnoc_axi", "qdss";
			mx-supply = <0x97>;
			cx-supply = <0x98>;
			pll-supply = <0x5d>;
			resets = <0x1b 0x69>;
			reset-names = "mss_restart";
			qcom,halt-regs = <0x13 0x23000 0x25000 0x24000>;
			qcom,smem-states = <0x99 0x0>;
			qcom,smem-state-names = "stop";
			status = "okay";

			mba {
				memory-region = <0x9a>;
			};

			mpss {
				memory-region = <0x9b>;
			};

			smd-edge {
				interrupts = <0x0 0x1c1 0x1>;
				label = "modem";
				mboxes = <0x17 0xc>;
				qcom,smd-edge = <0x0>;
				qcom,remote-pid = <0x1>;
			};
		};

		i2c@07577000 {
			label = "LS-I2C0";
			status = "disabled";
		};

		ufsphy@627000 {
			status = "okay";
		};

		wlan-en-1-8v {
			pinctrl-names = "default";
			pinctrl-0 = <0x9c>;
			compatible = "regulator-fixed";
			regulator-name = "wlan-en-regulator";
			regulator-min-microvolt = <0x1b7740>;
			regulator-max-microvolt = <0x1b7740>;
			gpio = <0x11 0x8 0x0>;
			startup-delay-us = <0x11170>;
			enable-active-high;
			phandle = <0x80>;
		};

		i2c@075ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x75ba000 0x1000>;
			interrupts = <0x0 0x6a 0x0>;
			clocks = <0x1b 0x81 0x1b 0x93>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x9d>;
			pinctrl-1 = <0x9e>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "okay";

			tca9535@20 {
				compatible = "ti,tca9535";
				reg = <0x20>;
				tca9535,invert = [00 00];
				tca9535,output = [fe ff];
				tca9535,config = [aa ff];
				gpio-controller;
				#gpio-cells = <0x2>;
				status = "okay";
				phandle = <0x9f>;
			};
		};

		i2c@075b5000 {
			label = "HS-I2C2";
			status = "ok";

			analogix_i2c@2c {
				compatible = "analogix,anx7625";
				status = "ok";
				reg = <0x2c>;
				interrupt-parent = <0x52>;
				interrupts = <0x4e 0x0 0x91 0x0>;
				analogix,p-on-gpio = <0x52 0x1c 0x0>;
				analogix,reset-gpio = <0x52 0x1b 0x0>;
				analogix,v33-ctrl-gpio = <0x52 0x95 0x0>;
				analogix,usb-id-gpio = <0x52 0x4a 0x0>;
				analogix,pmic-vbus-detect-gpio = <0x52 0x54 0x0>;
				analogix,source-or-sink-gpio = <0x52 0x94 0x0>;
				analogix,5v-or-9v-gpio = <0x52 0x8e 0x0>;
				analogix,intr-comm-gpio = <0x52 0x4e 0x0>;
				analogix,cbl-det-gpio = <0x52 0x91 0x0>;
				analogix,i2c-pull-up = <0x1>;
			};
		};

		fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "camera_vdddo";
			regulator-min-microvolt = <0x1b7740>;
			regulator-max-microvolt = <0x1b7740>;
			regulator-always-on;
			phandle = <0xa1>;
		};

		fixedregulator@1 {
			compatible = "regulator-fixed";
			regulator-name = "camera_vdda";
			regulator-min-microvolt = <0x2ab980>;
			regulator-max-microvolt = <0x2ab980>;
			regulator-always-on;
			phandle = <0xa2>;
		};

		fixedregulator@2 {
			compatible = "regulator-fixed";
			regulator-name = "camera_vddd";
			regulator-min-microvolt = <0x16e360>;
			regulator-max-microvolt = <0x16e360>;
			regulator-always-on;
			phandle = <0xa3>;
		};

		cci@a0c000 {
			status = "ok";

			camera_board@3c {
				compatible = "ovti,ov5645";
				reg = <0x3c>;
				enable-gpios = <0x9f 0x6 0x0>;
				reset-gpios = <0x52 0x87 0x1>;
				pinctrl-names = "default";
				pinctrl-0 = <0xa0>;
				clocks = <0x63 0x86>;
				clock-names = "xclk";
				clock-frequency = <0x16e3600>;
				vdddo-supply = <0xa1>;
				vdda-supply = <0xa2>;
				vddd-supply = <0xa3>;
				status = "ok";

				port {

					endpoint {
						clock-lanes = <0x1>;
						data-lanes = <0x0 0x2>;
						remote-endpoint = <0xa4>;
						phandle = <0x6d>;
					};
				};
			};
		};

		usb3-id {
			compatible = "linux,extcon-usb-gpio";
			id-gpio = <0x11 0x16 0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0xa5>;
			phandle = <0x68>;
		};
	};

	sound {
		compatible = "qcom,apq8096-sndcard";
		model = "DB820c";
		audio-routing = "RX_BIAS", "MCLK", "MIC BIAS1", "MCLK", "MIC BIAS2", "MCLK", "MIC BIAS3", "MCLK", "MIC BIAS4", "MCLK", "AMIC1", "MIC BIAS2", "AMIC2", "MIC BIAS2", "AMIC3", "MIC BIAS2", "AMIC4", "MIC BIAS2", "AMIC5", "MIC BIAS2", "AMIC6", "MIC BIAS2", "DMIC2", "MIC BIAS1", "DMIC3", "MIC BIAS1", "DMIC4", "MIC BIAS3", "DMIC5", "MIC BIAS3";

		mm1-dai-link {
			link-name = "MultiMedia1";

			cpu {
				sound-dai = <0xa6 0x0>;
			};
		};

		mm2-dai-link {
			link-name = "MultiMedia2";

			cpu {
				sound-dai = <0xa6 0x1>;
			};
		};

		mm3-dai-link {
			link-name = "MultiMedia3";

			cpu {
				sound-dai = <0xa6 0x2>;
			};
		};

		hdmi-dai-link {
			link-name = "HDMI Playback";

			cpu {
				sound-dai = <0xa7 0x1>;
			};

			platform {
				sound-dai = <0xa8>;
			};

			codec {
				sound-dai = <0xa9 0x0>;
			};
		};

		slim-dai-link {
			link-name = "SLIM Playback";

			cpu {
				sound-dai = <0xa7 0xe>;
			};

			platform {
				sound-dai = <0xa8>;
			};

			codec {
				sound-dai = <0xaa 0x6>;
			};
		};

		slimcap-dai-link {
			link-name = "SLIM Capture";

			cpu {
				sound-dai = <0xa7 0x3>;
			};

			platform {
				sound-dai = <0xa8>;
			};

			codec {
				sound-dai = <0xaa 0x1>;
			};
		};
	};

	adsp-pil {
		compatible = "qcom,msm8996-adsp-pil";
		interrupts-extended = <0x1 0x0 0xa2 0x1 0xab 0x0 0x1 0xab 0x1 0x1 0xab 0x2 0x1 0xab 0x3 0x1>;
		interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
		clocks = <0x49>;
		clock-names = "xo";
		memory-region = <0xac>;
		qcom,smem-states = <0xad 0x0>;
		qcom,smem-state-names = "stop";

		smd-edge {
			interrupts = <0x0 0x9c 0x1>;
			label = "lpass";
			mboxes = <0x17 0x8>;
			qcom,smd-edge = <0x1>;
			qcom,remote-pid = <0x2>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			fastrpc {
				compatible = "qcom,fastrpc";
				qcom,smd-channels = "fastrpcsmd-apps-dsp";
				label = "adsp";
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				cb@8 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <0x8>;
					iommus = <0xae 0x8>;
				};

				cb@9 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <0x9>;
					iommus = <0xae 0x9>;
				};

				cb@10 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <0xa>;
					iommus = <0xae 0xa>;
				};

				cb@11 {
					reg = <0xb>;
					compatible = "qcom,fastrpc-compute-cb";
					iommus = <0xae 0xb>;
				};

				cb@12 {
					reg = <0xc>;
					compatible = "qcom,fastrpc-compute-cb";
					iommus = <0xae 0xc>;
				};

				cb@5 {
					reg = <0x5>;
					compatible = "qcom,fastrpc-compute-cb";
					iommus = <0xae 0x5>;
				};

				cb@6 {
					reg = <0x6>;
					compatible = "qcom,fastrpc-compute-cb";
					iommus = <0xae 0x6>;
				};

				cb@7 {
					reg = <0x7>;
					compatible = "qcom,fastrpc-compute-cb";
					iommus = <0xae 0x7>;
				};
			};

			apr {
				power-domains = <0x1b 0x2>;
				compatible = "qcom,apr-v2";
				qcom,smd-channels = "apr_audio_svc";
				qcom,apr-domain = <0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				q6core {
					reg = <0x3>;
					compatible = "qcom,q6core";
				};

				q6afe {
					compatible = "qcom,q6afe";
					reg = <0x4>;

					dais {
						compatible = "qcom,q6afe-dais";
						#address-cells = <0x1>;
						#size-cells = <0x0>;
						#sound-dai-cells = <0x1>;
						phandle = <0xa7>;

						hdmi@1 {
							reg = <0x1>;
						};
					};
				};

				q6asm {
					compatible = "qcom,q6asm";
					reg = <0x7>;

					dais {
						compatible = "qcom,q6asm-dais";
						#sound-dai-cells = <0x1>;
						iommus = <0xae 0x1>;
						phandle = <0xa6>;
					};
				};

				q6adm {
					compatible = "qcom,q6adm";
					reg = <0x8>;

					routing {
						compatible = "qcom,q6adm-routing";
						#sound-dai-cells = <0x0>;
						phandle = <0xa8>;
					};
				};
			};
		};
	};

	adsp-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <0x1bb 0x1ad>;
		interrupts = <0x0 0x9e 0x1>;
		mboxes = <0x17 0xa>;
		qcom,local-pid = <0x0>;
		qcom,remote-pid = <0x2>;

		master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <0x1>;
			phandle = <0xad>;
		};

		slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xab>;
		};
	};

	modem-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <0x1b3 0x1ac>;
		interrupts = <0x0 0x1c3 0x1>;
		mboxes = <0x17 0xe>;
		qcom,local-pid = <0x0>;
		qcom,remote-pid = <0x1>;

		master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <0x1>;
			phandle = <0x99>;
		};

		slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x96>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <0x1e1 0x1ae>;
		interrupts = <0x0 0xb2 0x1>;
		mboxes = <0x17 0x1a>;
		qcom,local-pid = <0x0>;
		qcom,remote-pid = <0x3>;

		slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <0x1>;
		};
	};

	aliases {
		serial0 = "/soc/serial@75b0000";
		serial1 = "/soc/serial@75b1000";
		serial2 = "/soc/serial@7570000";
		i2c0 = "/soc/i2c@7577000";
		i2c1 = "/soc/i2c@75b6000";
		i2c2 = "/soc/i2c@75b5000";
		spi0 = "/soc/spi@7575000";
		spi1 = "/soc/spi@75ba000";
	};
};