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Oct 28th, 2018
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  1. module machine(clk, reset);
  2.    input        clk, reset;
  3.  
  4.    wire [31:0]  PC;
  5.    wire [31:2]  next_PC, PC_plus4, PC_target;
  6.    wire [31:0]  inst;
  7.  
  8.    wire [31:0]  imm = {{ 16{inst[15]} }, inst[15:0] };  // sign-extended immediate
  9.    wire [4:0]   rs = inst[25:21];
  10.    wire [4:0]   rt = inst[20:16];
  11.    wire [4:0]   rd = inst[15:11];
  12.  
  13.    wire [4:0]   wr_regnum;
  14.    wire [2:0]   ALUOp;
  15.  
  16.    wire         RegWrite, BEQ, ALUSrc, MemRead, MemWrite, MemToReg, RegDst, MFC0, MTC0, ERET;
  17.    wire         PCSrc, zero, negative;
  18.    wire         TakenInterrupt,TimerInterrupt,TimerAddress;
  19.    wire [31:0]  rd1_data, rd2_data, B_data, alu_out_data, load_data, wr_data, old_wr_data, rd_data, cycle;
  20.    wire [29:0] newmux1_out, real_next_PC, EPC;
  21.    wire        realMemRead,realMemWrite, NotIO;
  22.  
  23.  
  24.    register #(30, 30'h100000) PC_reg(PC[31:2], real_next_PC, clk, /* enable */1'b1, reset);
  25.    assign PC[1:0] = 2'b0;  // bottom bits hard coded to 00
  26.    adder30 next_PC_adder(PC_plus4, PC[31:2], 30'h1);
  27.    adder30 target_PC_adder(PC_target, PC_plus4, imm[29:0]);
  28.    mux2v #(30) branch_mux(next_PC, PC_plus4, PC_target, PCSrc);
  29.    assign PCSrc = BEQ & zero;
  30.  
  31.    instruction_memory imem (inst, PC[31:2]);
  32.  
  33.    mips_decode decode(ALUOp, RegWrite, BEQ, ALUSrc, MemRead, MemWrite, MemToReg, RegDst, MFC0, MTC0, ERET,
  34.                       inst);
  35.  
  36.    regfile rf (rd1_data, rd2_data,
  37.                rs, rt, wr_regnum, wr_data,
  38.                RegWrite, clk, reset);
  39.  
  40.    mux2v #(32) imm_mux(B_data, rd2_data, imm, ALUSrc);
  41.    alu32 alu(alu_out_data, zero, negative, ALUOp, rd1_data, B_data);
  42.  
  43. assign NotIO = ~TimerAddress;
  44. assign realMemRead = MemRead & NotIO;
  45. assign realMemWrite = MemWrite & NotIO;
  46.  
  47.    data_mem data_memory(load_data, alu_out_data, rd2_data, realMemRead, realMemWrite, clk, reset);
  48.  
  49.    wire [31:0] driven_by_two;
  50.    assign driven_by_two = load_data;
  51.    assign driven_by_two = cycle;
  52.  
  53.    mux2v #(32) wb_mux(old_wr_data, alu_out_data, driven_by_two, MemToReg);
  54.    mux2v #(5) rd_mux(wr_regnum, rt, rd, RegDst);
  55.  
  56. cp0 thecp0(rd_data,EPC,TakenInterrupt,rd2_data, wr_regnum, next_PC,
  57.           MTC0, ERET, TimerInterrupt, clk, reset);
  58.  
  59. timer thetimer(TimerInterrupt, cycle, TimerAddress,
  60.              rd2_data, alu_out_data, MemRead, MemWrite, clk, reset);
  61.  
  62. mux2v #(32) realwrmux(wr_data, old_wr_data,rd_data,MFC0);
  63. mux2v #(30) epcmux(newmux1_out,next_PC, EPC, ERET);
  64.  
  65. wire[31:0] tempNum = 32'h80000180;
  66. mux2v #(30) errormux(real_next_PC,newmux1_out,tempNum[31:2],TakenInterrupt);
  67.  
  68. endmodule // machine
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