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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. interrupt-parent = <0x1>;
  7. model = "NextThing C.H.I.P.";
  8. compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
  9.  
  10. chosen {
  11. #address-cells = <0x1>;
  12. #size-cells = <0x1>;
  13. ranges;
  14. stdout-path = "serial0:115200n8";
  15.  
  16. framebuffer@0 {
  17. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  18. allwinner,pipeline = "de_be0-lcd0";
  19. clocks = <0x2 0x24 0x2 0x2c 0x3 0x4 0x5 0x1a>;
  20. status = "disabled";
  21. };
  22.  
  23. framebuffer@1 {
  24. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  25. allwinner,pipeline = "de_be0-lcd0-tve0";
  26. clocks = <0x2 0x22 0x2 0x24 0x2 0x2c 0x3 0x6 0x5 0x1a>;
  27. status = "disabled";
  28. };
  29. };
  30.  
  31. aliases {
  32. i2c0 = "/soc@01c00000/i2c@01c2ac00";
  33. i2c1 = "/soc@01c00000/i2c@01c2b000";
  34. i2c2 = "/soc@01c00000/i2c@01c2b400";
  35. serial0 = "/soc@01c00000/serial@01c28400";
  36. serial1 = "/soc@01c00000/serial@01c28c00";
  37. };
  38.  
  39. memory {
  40. device_type = "memory";
  41. reg = <0x0 0x0>;
  42. };
  43.  
  44. cpus {
  45. #address-cells = <0x1>;
  46. #size-cells = <0x0>;
  47.  
  48. cpu@0 {
  49. device_type = "cpu";
  50. compatible = "arm,cortex-a8";
  51. reg = <0x0>;
  52. clocks = <0x7>;
  53. clock-latency = <0x3b9b0>;
  54. operating-points = <0xf6180 0x155cc0 0xdea80 0x149970 0xd2f00 0x13d620 0x98580 0x124f80 0x8ca00 0x124f80 0x69780 0x124f80>;
  55. #cooling-cells = <0x2>;
  56. cooling-min-level = <0x0>;
  57. cooling-max-level = <0x5>;
  58. cpu-supply = <0x8>;
  59. linux,phandle = <0x44>;
  60. phandle = <0x44>;
  61. };
  62. };
  63.  
  64. clocks {
  65. #address-cells = <0x1>;
  66. #size-cells = <0x1>;
  67. ranges;
  68.  
  69. dummy {
  70. #clock-cells = <0x0>;
  71. compatible = "fixed-clock";
  72. clock-frequency = <0x0>;
  73. linux,phandle = <0xf>;
  74. phandle = <0xf>;
  75. };
  76.  
  77. clk@01c20050 {
  78. #clock-cells = <0x0>;
  79. compatible = "allwinner,sun4i-a10-osc-clk";
  80. reg = <0x1c20050 0x4>;
  81. clock-frequency = <0x16e3600>;
  82. clock-output-names = "osc24M";
  83. linux,phandle = <0x9>;
  84. phandle = <0x9>;
  85. };
  86.  
  87. osc3M_clk {
  88. compatible = "fixed-factor-clock";
  89. #clock-cells = <0x0>;
  90. clock-div = <0x8>;
  91. clock-mult = <0x1>;
  92. clocks = <0x9>;
  93. clock-output-names = "osc3M";
  94. linux,phandle = <0xa>;
  95. phandle = <0xa>;
  96. };
  97.  
  98. clk@0 {
  99. #clock-cells = <0x0>;
  100. compatible = "fixed-clock";
  101. clock-frequency = <0x8000>;
  102. clock-output-names = "osc32k";
  103. linux,phandle = <0xd>;
  104. phandle = <0xd>;
  105. };
  106.  
  107. clk@01c20000 {
  108. #clock-cells = <0x0>;
  109. compatible = "allwinner,sun4i-a10-pll1-clk";
  110. reg = <0x1c20000 0x4>;
  111. clocks = <0x9>;
  112. clock-output-names = "pll1";
  113. linux,phandle = <0xe>;
  114. phandle = <0xe>;
  115. };
  116.  
  117. clk@01c20008 {
  118. #clock-cells = <0x1>;
  119. compatible = "allwinner,sun5i-a13-pll2-clk";
  120. reg = <0x1c20008 0x8>;
  121. clocks = <0x9>;
  122. clock-output-names = "pll2-1x", "pll2-2x", "pll2-4x", "pll2-8x";
  123. linux,phandle = <0x14>;
  124. phandle = <0x14>;
  125. };
  126.  
  127. clk@01c20010 {
  128. #clock-cells = <0x0>;
  129. compatible = "allwinner,sun4i-a10-pll3-clk";
  130. reg = <0x1c20010 0x4>;
  131. clocks = <0xa>;
  132. clock-output-names = "pll3";
  133. linux,phandle = <0xb>;
  134. phandle = <0xb>;
  135. };
  136.  
  137. pll3x2_clk {
  138. compatible = "fixed-factor-clock";
  139. #clock-cells = <0x0>;
  140. clock-div = <0x1>;
  141. clock-mult = <0x2>;
  142. clocks = <0xb>;
  143. clock-output-names = "pll3-2x";
  144. linux,phandle = <0x17>;
  145. phandle = <0x17>;
  146. };
  147.  
  148. clk@01c20018 {
  149. #clock-cells = <0x0>;
  150. compatible = "allwinner,sun4i-a10-pll1-clk";
  151. reg = <0x1c20018 0x4>;
  152. clocks = <0x9>;
  153. clock-output-names = "pll4";
  154. linux,phandle = <0x19>;
  155. phandle = <0x19>;
  156. };
  157.  
  158. clk@01c20020 {
  159. #clock-cells = <0x1>;
  160. compatible = "allwinner,sun4i-a10-pll5-clk";
  161. reg = <0x1c20020 0x4>;
  162. clocks = <0x9>;
  163. clock-output-names = "pll5_ddr", "pll5_other";
  164. linux,phandle = <0x13>;
  165. phandle = <0x13>;
  166. };
  167.  
  168. clk@01c20028 {
  169. #clock-cells = <0x1>;
  170. compatible = "allwinner,sun4i-a10-pll6-clk";
  171. reg = <0x1c20028 0x4>;
  172. clocks = <0x9>;
  173. clock-output-names = "pll6_sata", "pll6_other", "pll6";
  174. linux,phandle = <0x11>;
  175. phandle = <0x11>;
  176. };
  177.  
  178. clk@01c20030 {
  179. #clock-cells = <0x0>;
  180. compatible = "allwinner,sun4i-a10-pll3-clk";
  181. reg = <0x1c20030 0x4>;
  182. clocks = <0xa>;
  183. clock-output-names = "pll7";
  184. linux,phandle = <0xc>;
  185. phandle = <0xc>;
  186. };
  187.  
  188. pll7x2_clk {
  189. compatible = "fixed-factor-clock";
  190. #clock-cells = <0x0>;
  191. clock-div = <0x1>;
  192. clock-mult = <0x2>;
  193. clocks = <0xc>;
  194. clock-output-names = "pll7-2x";
  195. linux,phandle = <0x18>;
  196. phandle = <0x18>;
  197. };
  198.  
  199. cpu@01c20054 {
  200. #clock-cells = <0x0>;
  201. compatible = "allwinner,sun4i-a10-cpu-clk";
  202. reg = <0x1c20054 0x4>;
  203. clocks = <0xd 0x9 0xe 0xf>;
  204. clock-output-names = "cpu";
  205. linux,phandle = <0x7>;
  206. phandle = <0x7>;
  207. };
  208.  
  209. axi@01c20054 {
  210. #clock-cells = <0x0>;
  211. compatible = "allwinner,sun4i-a10-axi-clk";
  212. reg = <0x1c20054 0x4>;
  213. clocks = <0x7>;
  214. clock-output-names = "axi";
  215. linux,phandle = <0x10>;
  216. phandle = <0x10>;
  217. };
  218.  
  219. ahb@01c20054 {
  220. #clock-cells = <0x0>;
  221. compatible = "allwinner,sun5i-a13-ahb-clk";
  222. reg = <0x1c20054 0x4>;
  223. clocks = <0x10 0x7 0x11 0x1>;
  224. clock-output-names = "ahb";
  225. assigned-clocks = <0x12>;
  226. assigned-clock-parents = <0x11 0x1>;
  227. linux,phandle = <0x12>;
  228. phandle = <0x12>;
  229. };
  230.  
  231. apb0@01c20054 {
  232. #clock-cells = <0x0>;
  233. compatible = "allwinner,sun4i-a10-apb0-clk";
  234. reg = <0x1c20054 0x4>;
  235. clocks = <0x12>;
  236. clock-output-names = "apb0";
  237. linux,phandle = <0x15>;
  238. phandle = <0x15>;
  239. };
  240.  
  241. clk@01c20058 {
  242. #clock-cells = <0x0>;
  243. compatible = "allwinner,sun4i-a10-apb1-clk";
  244. reg = <0x1c20058 0x4>;
  245. clocks = <0x9 0x11 0x1 0xd>;
  246. clock-output-names = "apb1";
  247. linux,phandle = <0x16>;
  248. phandle = <0x16>;
  249. };
  250.  
  251. clk@01c2005c {
  252. #clock-cells = <0x1>;
  253. compatible = "allwinner,sun4i-a10-axi-gates-clk";
  254. reg = <0x1c2005c 0x4>;
  255. clocks = <0x10>;
  256. clock-indices = <0x0>;
  257. clock-output-names = "axi_dram";
  258. linux,phandle = <0x4f>;
  259. phandle = <0x4f>;
  260. };
  261.  
  262. clk@01c20080 {
  263. #clock-cells = <0x0>;
  264. compatible = "allwinner,sun4i-a10-mod0-clk";
  265. reg = <0x1c20080 0x4>;
  266. clocks = <0x9 0x11 0x1 0x13 0x1>;
  267. clock-output-names = "nand";
  268. linux,phandle = <0x1a>;
  269. phandle = <0x1a>;
  270. };
  271.  
  272. clk@01c20084 {
  273. #clock-cells = <0x0>;
  274. compatible = "allwinner,sun4i-a10-mod0-clk";
  275. reg = <0x1c20084 0x4>;
  276. clocks = <0x9 0x11 0x1 0x13 0x1>;
  277. clock-output-names = "ms";
  278. linux,phandle = <0x50>;
  279. phandle = <0x50>;
  280. };
  281.  
  282. clk@01c20088 {
  283. #clock-cells = <0x1>;
  284. compatible = "allwinner,sun4i-a10-mmc-clk";
  285. reg = <0x1c20088 0x4>;
  286. clocks = <0x9 0x11 0x1 0x13 0x1>;
  287. clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
  288. linux,phandle = <0x21>;
  289. phandle = <0x21>;
  290. };
  291.  
  292. clk@01c2008c {
  293. #clock-cells = <0x1>;
  294. compatible = "allwinner,sun4i-a10-mmc-clk";
  295. reg = <0x1c2008c 0x4>;
  296. clocks = <0x9 0x11 0x1 0x13 0x1>;
  297. clock-output-names = "mmc1", "mmc1_output", "mmc1_sample";
  298. linux,phandle = <0x25>;
  299. phandle = <0x25>;
  300. };
  301.  
  302. clk@01c20090 {
  303. #clock-cells = <0x1>;
  304. compatible = "allwinner,sun4i-a10-mmc-clk";
  305. reg = <0x1c20090 0x4>;
  306. clocks = <0x9 0x11 0x1 0x13 0x1>;
  307. clock-output-names = "mmc2", "mmc2_output", "mmc2_sample";
  308. linux,phandle = <0x26>;
  309. phandle = <0x26>;
  310. };
  311.  
  312. clk@01c20098 {
  313. #clock-cells = <0x0>;
  314. compatible = "allwinner,sun4i-a10-mod0-clk";
  315. reg = <0x1c20098 0x4>;
  316. clocks = <0x9 0x11 0x1 0x13 0x1>;
  317. clock-output-names = "ts";
  318. linux,phandle = <0x51>;
  319. phandle = <0x51>;
  320. };
  321.  
  322. clk@01c2009c {
  323. #clock-cells = <0x0>;
  324. compatible = "allwinner,sun4i-a10-mod0-clk";
  325. reg = <0x1c2009c 0x4>;
  326. clocks = <0x9 0x11 0x1 0x13 0x1>;
  327. clock-output-names = "ss";
  328. linux,phandle = <0x52>;
  329. phandle = <0x52>;
  330. };
  331.  
  332. clk@01c200a0 {
  333. #clock-cells = <0x0>;
  334. compatible = "allwinner,sun4i-a10-mod0-clk";
  335. reg = <0x1c200a0 0x4>;
  336. clocks = <0x9 0x11 0x1 0x13 0x1>;
  337. clock-output-names = "spi0";
  338. linux,phandle = <0x1f>;
  339. phandle = <0x1f>;
  340. };
  341.  
  342. clk@01c200a4 {
  343. #clock-cells = <0x0>;
  344. compatible = "allwinner,sun4i-a10-mod0-clk";
  345. reg = <0x1c200a4 0x4>;
  346. clocks = <0x9 0x11 0x1 0x13 0x1>;
  347. clock-output-names = "spi1";
  348. linux,phandle = <0x20>;
  349. phandle = <0x20>;
  350. };
  351.  
  352. clk@01c200a8 {
  353. #clock-cells = <0x0>;
  354. compatible = "allwinner,sun4i-a10-mod0-clk";
  355. reg = <0x1c200a8 0x4>;
  356. clocks = <0x9 0x11 0x1 0x13 0x1>;
  357. clock-output-names = "spi2";
  358. linux,phandle = <0x2f>;
  359. phandle = <0x2f>;
  360. };
  361.  
  362. clk@01c200b0 {
  363. #clock-cells = <0x0>;
  364. compatible = "allwinner,sun4i-a10-mod0-clk";
  365. reg = <0x1c200b0 0x4>;
  366. clocks = <0x9 0x11 0x1 0x13 0x1>;
  367. clock-output-names = "ir0";
  368. linux,phandle = <0x53>;
  369. phandle = <0x53>;
  370. };
  371.  
  372. clk@01c200cc {
  373. #clock-cells = <0x1>;
  374. #reset-cells = <0x1>;
  375. compatible = "allwinner,sun5i-a13-usb-clk";
  376. reg = <0x1c200cc 0x4>;
  377. clocks = <0x11 0x1>;
  378. clock-output-names = "usb_ohci0", "usb_phy";
  379. linux,phandle = <0x29>;
  380. phandle = <0x29>;
  381. };
  382.  
  383. clk@01c20140 {
  384. #clock-cells = <0x0>;
  385. compatible = "allwinner,sun4i-a10-codec-clk";
  386. reg = <0x1c20140 0x4>;
  387. clocks = <0x14 0x0>;
  388. clock-output-names = "codec";
  389. linux,phandle = <0x32>;
  390. phandle = <0x32>;
  391. };
  392.  
  393. clk@01c2015c {
  394. #clock-cells = <0x0>;
  395. compatible = "allwinner,sun5i-a13-mbus-clk";
  396. reg = <0x1c2015c 0x4>;
  397. clocks = <0x9 0x11 0x1 0x13 0x1>;
  398. clock-output-names = "mbus";
  399. linux,phandle = <0x54>;
  400. phandle = <0x54>;
  401. };
  402.  
  403. clk@01c20060 {
  404. #clock-cells = <0x1>;
  405. compatible = "allwinner,sun5i-a13-ahb-gates-clk";
  406. reg = <0x1c20060 0x8>;
  407. clocks = <0x12>;
  408. clock-indices = <0x0 0x1 0x2 0x5 0x6 0x7 0x8 0x9 0xa 0xd 0xe 0x14 0x15 0x16 0x1c 0x20 0x22 0x24 0x28 0x2c 0x2e 0x33 0x34>;
  409. clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", "ahb_ve", "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
  410. linux,phandle = <0x2>;
  411. phandle = <0x2>;
  412. };
  413.  
  414. clk@01c20068 {
  415. #clock-cells = <0x1>;
  416. compatible = "allwinner,sun5i-a13-apb0-gates-clk";
  417. reg = <0x1c20068 0x4>;
  418. clocks = <0x15>;
  419. clock-indices = <0x0 0x5 0x6>;
  420. clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
  421. linux,phandle = <0x30>;
  422. phandle = <0x30>;
  423. };
  424.  
  425. clk@01c2006c {
  426. #clock-cells = <0x1>;
  427. compatible = "allwinner,sun5i-a13-apb1-gates-clk";
  428. reg = <0x1c2006c 0x4>;
  429. clocks = <0x16>;
  430. clock-indices = <0x0 0x1 0x2 0x11 0x13>;
  431. clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_uart1", "apb1_uart3";
  432. linux,phandle = <0x33>;
  433. phandle = <0x33>;
  434. };
  435.  
  436. clk@01c20100 {
  437. #clock-cells = <0x1>;
  438. compatible = "allwinner,sun5i-a13-dram-gates-clk", "allwinner,sun4i-a10-gates-clk";
  439. reg = <0x1c20100 0x4>;
  440. clocks = <0x13 0x0>;
  441. clock-indices = <0x0 0x1 0x19 0x1a 0x1d 0x1f>;
  442. clock-output-names = "dram_ve", "dram_csi", "dram_de_fe", "dram_de_be", "dram_ace", "dram_iep";
  443. linux,phandle = <0x5>;
  444. phandle = <0x5>;
  445. };
  446.  
  447. clk@01c20104 {
  448. #clock-cells = <0x0>;
  449. #reset-cells = <0x0>;
  450. compatible = "allwinner,sun4i-a10-display-clk";
  451. reg = <0x1c20104 0x4>;
  452. clocks = <0xb 0xc 0x13 0x1>;
  453. clock-output-names = "de-be";
  454. linux,phandle = <0x3>;
  455. phandle = <0x3>;
  456. };
  457.  
  458. clk@01c2010c {
  459. #clock-cells = <0x0>;
  460. #reset-cells = <0x0>;
  461. compatible = "allwinner,sun4i-a10-display-clk";
  462. reg = <0x1c2010c 0x4>;
  463. clocks = <0xb 0xc 0x13 0x1>;
  464. clock-output-names = "de-fe";
  465. linux,phandle = <0x3c>;
  466. phandle = <0x3c>;
  467. };
  468.  
  469. clk@01c20118 {
  470. #clock-cells = <0x0>;
  471. #reset-cells = <0x1>;
  472. compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
  473. reg = <0x1c20118 0x4>;
  474. clocks = <0xb 0xc 0x17 0x18>;
  475. clock-output-names = "tcon-ch0-sclk";
  476. linux,phandle = <0x4>;
  477. phandle = <0x4>;
  478. };
  479.  
  480. clk@01c2012c {
  481. #clock-cells = <0x0>;
  482. compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
  483. reg = <0x1c2012c 0x4>;
  484. clocks = <0xb 0xc 0x17 0x18>;
  485. clock-output-names = "tcon-ch1-sclk";
  486. linux,phandle = <0x6>;
  487. phandle = <0x6>;
  488. };
  489.  
  490. clk@01c20154 {
  491. #clock-cells = <0x0>;
  492. #reset-cells = <0x0>;
  493. compatible = "allwinner,sun4i-a10-gpu-clk";
  494. reg = <0x1c20154 0x4>;
  495. clocks = <0xb 0x19 0x13 0x1 0xc 0x18>;
  496. clock-output-names = "mali";
  497. linux,phandle = <0x41>;
  498. phandle = <0x41>;
  499. };
  500. };
  501.  
  502. soc@01c00000 {
  503. compatible = "simple-bus";
  504. #address-cells = <0x1>;
  505. #size-cells = <0x1>;
  506. ranges;
  507.  
  508. sram-controller@01c00000 {
  509. compatible = "allwinner,sun4i-a10-sram-controller";
  510. reg = <0x1c00000 0x30>;
  511. #address-cells = <0x1>;
  512. #size-cells = <0x1>;
  513. ranges;
  514.  
  515. sram@00000000 {
  516. compatible = "mmio-sram";
  517. reg = <0x0 0xc000>;
  518. #address-cells = <0x1>;
  519. #size-cells = <0x1>;
  520. ranges = <0x0 0x0 0xc000>;
  521. linux,phandle = <0x55>;
  522. phandle = <0x55>;
  523. };
  524.  
  525. sram@00010000 {
  526. compatible = "mmio-sram";
  527. reg = <0x10000 0x1000>;
  528. #address-cells = <0x1>;
  529. #size-cells = <0x1>;
  530. ranges = <0x0 0x10000 0x1000>;
  531. linux,phandle = <0x56>;
  532. phandle = <0x56>;
  533.  
  534. sram-section@0000 {
  535. compatible = "allwinner,sun4i-a10-sram-d";
  536. reg = <0x0 0x1000>;
  537. status = "okay";
  538. linux,phandle = <0x28>;
  539. phandle = <0x28>;
  540. };
  541. };
  542. };
  543.  
  544. dma-controller@01c02000 {
  545. compatible = "allwinner,sun4i-a10-dma";
  546. reg = <0x1c02000 0x1000>;
  547. interrupts = <0x1b>;
  548. clocks = <0x2 0x6>;
  549. #dma-cells = <0x2>;
  550. linux,phandle = <0x1e>;
  551. phandle = <0x1e>;
  552. };
  553.  
  554. nand@01c03000 {
  555. compatible = "allwinner,sun4i-a10-nand";
  556. reg = <0x1c03000 0x1000>;
  557. interrupts = <0x25>;
  558. clocks = <0x2 0xd 0x1a>;
  559. clock-names = "ahb", "mod";
  560. #address-cells = <0x1>;
  561. #size-cells = <0x0>;
  562. status = "okay";
  563. pinctrl-names = "default";
  564. pinctrl-0 = <0x1b 0x1c 0x1d>;
  565. dmas = <0x1e 0x1 0x3>;
  566. dma-names = "rxtx";
  567. linux,phandle = <0x57>;
  568. phandle = <0x57>;
  569.  
  570. nand@0 {
  571. #address-cells = <0x2>;
  572. #size-cells = <0x2>;
  573. reg = <0x0>;
  574. allwinner,rb = <0x0>;
  575. nand-ecc-mode = "hw";
  576.  
  577. spl@0 {
  578. label = "SPL";
  579. reg = <0x0 0x0 0x0 0x400000>;
  580. };
  581.  
  582. spl-backup@400000 {
  583. label = "SPL.backup";
  584. reg = <0x0 0x400000 0x0 0x400000>;
  585. };
  586.  
  587. u-boot@800000 {
  588. label = "U-Boot";
  589. reg = <0x0 0x800000 0x0 0x400000>;
  590. };
  591.  
  592. env@c00000 {
  593. label = "env";
  594. reg = <0x0 0xc00000 0x0 0x400000>;
  595. };
  596.  
  597. rootfs@1000000 {
  598. label = "rootfs";
  599. reg = <0x0 0x1000000 0x1 0xff000000>;
  600. };
  601. };
  602. };
  603.  
  604. spi@01c05000 {
  605. compatible = "allwinner,sun4i-a10-spi";
  606. reg = <0x1c05000 0x1000>;
  607. interrupts = <0xa>;
  608. clocks = <0x2 0x14 0x1f>;
  609. clock-names = "ahb", "mod";
  610. dmas = <0x1e 0x1 0x1b 0x1e 0x1 0x1a>;
  611. dma-names = "rx", "tx";
  612. status = "disabled";
  613. #address-cells = <0x1>;
  614. #size-cells = <0x0>;
  615. linux,phandle = <0x58>;
  616. phandle = <0x58>;
  617. };
  618.  
  619. spi@01c06000 {
  620. compatible = "allwinner,sun4i-a10-spi";
  621. reg = <0x1c06000 0x1000>;
  622. interrupts = <0xb>;
  623. clocks = <0x2 0x15 0x20>;
  624. clock-names = "ahb", "mod";
  625. dmas = <0x1e 0x1 0x9 0x1e 0x1 0x8>;
  626. dma-names = "rx", "tx";
  627. status = "disabled";
  628. #address-cells = <0x1>;
  629. #size-cells = <0x0>;
  630. linux,phandle = <0x59>;
  631. phandle = <0x59>;
  632. };
  633.  
  634. mmc@01c0f000 {
  635. compatible = "allwinner,sun5i-a13-mmc";
  636. reg = <0x1c0f000 0x1000>;
  637. clocks = <0x2 0x8 0x21 0x0 0x21 0x1 0x21 0x2>;
  638. clock-names = "ahb", "mmc", "output", "sample";
  639. interrupts = <0x20>;
  640. status = "okay";
  641. #address-cells = <0x1>;
  642. #size-cells = <0x0>;
  643. pinctrl-names = "default";
  644. pinctrl-0 = <0x22>;
  645. vmmc-supply = <0x23>;
  646. mmc-pwrseq = <0x24>;
  647. bus-width = <0x4>;
  648. non-removable;
  649. linux,phandle = <0x5a>;
  650. phandle = <0x5a>;
  651. };
  652.  
  653. mmc@01c10000 {
  654. compatible = "allwinner,sun5i-a13-mmc";
  655. reg = <0x1c10000 0x1000>;
  656. clocks = <0x2 0x9 0x25 0x0 0x25 0x1 0x25 0x2>;
  657. clock-names = "ahb", "mmc", "output", "sample";
  658. interrupts = <0x21>;
  659. status = "disabled";
  660. #address-cells = <0x1>;
  661. #size-cells = <0x0>;
  662. linux,phandle = <0x5b>;
  663. phandle = <0x5b>;
  664. };
  665.  
  666. mmc@01c11000 {
  667. compatible = "allwinner,sun5i-a13-mmc";
  668. reg = <0x1c11000 0x1000>;
  669. clocks = <0x2 0xa 0x26 0x0 0x26 0x1 0x26 0x2>;
  670. clock-names = "ahb", "mmc", "output", "sample";
  671. interrupts = <0x22>;
  672. status = "disabled";
  673. #address-cells = <0x1>;
  674. #size-cells = <0x0>;
  675. linux,phandle = <0x5c>;
  676. phandle = <0x5c>;
  677. };
  678.  
  679. usb@01c13000 {
  680. compatible = "allwinner,sun4i-a10-musb";
  681. reg = <0x1c13000 0x400>;
  682. clocks = <0x2 0x0>;
  683. interrupts = <0x26>;
  684. interrupt-names = "mc";
  685. phys = <0x27 0x0>;
  686. phy-names = "usb";
  687. extcon = <0x27 0x0>;
  688. allwinner,sram = <0x28 0x1>;
  689. status = "okay";
  690. dr_mode = "otg";
  691. linux,phandle = <0x5d>;
  692. phandle = <0x5d>;
  693. };
  694.  
  695. phy@01c13400 {
  696. #phy-cells = <0x1>;
  697. compatible = "allwinner,sun5i-a13-usb-phy";
  698. reg = <0x1c13400 0x10 0x1c14800 0x4>;
  699. reg-names = "phy_ctrl", "pmu1";
  700. clocks = <0x29 0x8>;
  701. clock-names = "usb_phy";
  702. resets = <0x29 0x0 0x29 0x1>;
  703. reset-names = "usb0_reset", "usb1_reset";
  704. status = "okay";
  705. pinctrl-names = "default";
  706. pinctrl-0 = <0x2a>;
  707. usb0_id_det-gpio = <0x2b 0x6 0x2 0x0>;
  708. usb0_vbus_power-supply = <0x2c>;
  709. usb0_vbus-supply = <0x2d>;
  710. usb1_vbus-supply = <0x2e>;
  711. linux,phandle = <0x27>;
  712. phandle = <0x27>;
  713. };
  714.  
  715. usb@01c14000 {
  716. compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
  717. reg = <0x1c14000 0x100>;
  718. interrupts = <0x27>;
  719. clocks = <0x2 0x1>;
  720. phys = <0x27 0x1>;
  721. phy-names = "usb";
  722. status = "okay";
  723. linux,phandle = <0x5e>;
  724. phandle = <0x5e>;
  725. };
  726.  
  727. usb@01c14400 {
  728. compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
  729. reg = <0x1c14400 0x100>;
  730. interrupts = <0x28>;
  731. clocks = <0x29 0x6 0x2 0x2>;
  732. phys = <0x27 0x1>;
  733. phy-names = "usb";
  734. status = "okay";
  735. linux,phandle = <0x5f>;
  736. phandle = <0x5f>;
  737. };
  738.  
  739. spi@01c17000 {
  740. compatible = "allwinner,sun4i-a10-spi";
  741. reg = <0x1c17000 0x1000>;
  742. interrupts = <0xc>;
  743. clocks = <0x2 0x16 0x2f>;
  744. clock-names = "ahb", "mod";
  745. dmas = <0x1e 0x1 0x1d 0x1e 0x1 0x1c>;
  746. dma-names = "rx", "tx";
  747. status = "disabled";
  748. #address-cells = <0x1>;
  749. #size-cells = <0x0>;
  750. linux,phandle = <0x60>;
  751. phandle = <0x60>;
  752. };
  753.  
  754. interrupt-controller@01c20400 {
  755. compatible = "allwinner,sun4i-a10-ic";
  756. reg = <0x1c20400 0x400>;
  757. interrupt-controller;
  758. #interrupt-cells = <0x1>;
  759. linux,phandle = <0x1>;
  760. phandle = <0x1>;
  761. };
  762.  
  763. pinctrl@01c20800 {
  764. reg = <0x1c20800 0x400>;
  765. interrupts = <0x1c>;
  766. clocks = <0x30 0x5>;
  767. gpio-controller;
  768. interrupt-controller;
  769. #interrupt-cells = <0x3>;
  770. #gpio-cells = <0x3>;
  771. compatible = "allwinner,sun5i-a13-pinctrl";
  772. linux,phandle = <0x2b>;
  773. phandle = <0x2b>;
  774.  
  775. i2c0@0 {
  776. allwinner,pins = "PB0", "PB1";
  777. allwinner,function = "i2c0";
  778. allwinner,drive = <0x0>;
  779. allwinner,pull = <0x0>;
  780. linux,phandle = <0x37>;
  781. phandle = <0x37>;
  782. };
  783.  
  784. i2c1@0 {
  785. allwinner,pins = "PB15", "PB16";
  786. allwinner,function = "i2c1";
  787. allwinner,drive = <0x0>;
  788. allwinner,pull = <0x0>;
  789. linux,phandle = <0x38>;
  790. phandle = <0x38>;
  791. };
  792.  
  793. i2c2@0 {
  794. allwinner,pins = "PB17", "PB18";
  795. allwinner,function = "i2c2";
  796. allwinner,drive = <0x0>;
  797. allwinner,pull = <0x0>;
  798. linux,phandle = <0x39>;
  799. phandle = <0x39>;
  800. };
  801.  
  802. lcd_rgb565@0 {
  803. allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD19", "PD20", "PD21", "PD22", "PD23", "PD24", "PD25", "PD26", "PD27";
  804. allwinner,function = "lcd0";
  805. allwinner,drive = <0x0>;
  806. allwinner,pull = <0x0>;
  807. linux,phandle = <0x61>;
  808. phandle = <0x61>;
  809. };
  810.  
  811. mmc0@0 {
  812. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  813. allwinner,function = "mmc0";
  814. allwinner,drive = <0x2>;
  815. allwinner,pull = <0x1>;
  816. linux,phandle = <0x22>;
  817. phandle = <0x22>;
  818. };
  819.  
  820. mmc2@0 {
  821. allwinner,pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15";
  822. allwinner,function = "mmc2";
  823. allwinner,drive = <0x2>;
  824. allwinner,pull = <0x1>;
  825. linux,phandle = <0x62>;
  826. phandle = <0x62>;
  827. };
  828.  
  829. nand_base0@0 {
  830. allwinner,pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15";
  831. allwinner,function = "nand0";
  832. allwinner,drive = <0x0>;
  833. allwinner,pull = <0x0>;
  834. linux,phandle = <0x1b>;
  835. phandle = <0x1b>;
  836. };
  837.  
  838. nand_cs@0 {
  839. allwinner,pins = "PC4";
  840. allwinner,function = "nand0";
  841. allwinner,drive = <0x0>;
  842. allwinner,pull = <0x0>;
  843. linux,phandle = <0x1c>;
  844. phandle = <0x1c>;
  845. };
  846.  
  847. nand_cs@1 {
  848. allwinner,pins = "PC3";
  849. allwinner,function = "nand0";
  850. allwinner,drive = <0x0>;
  851. allwinner,pull = <0x0>;
  852. linux,phandle = <0x63>;
  853. phandle = <0x63>;
  854. };
  855.  
  856. nand_rb@0 {
  857. allwinner,pins = "PC6";
  858. allwinner,function = "nand0";
  859. allwinner,drive = <0x0>;
  860. allwinner,pull = <0x0>;
  861. linux,phandle = <0x1d>;
  862. phandle = <0x1d>;
  863. };
  864.  
  865. nand_rb@1 {
  866. allwinner,pins = "PC7";
  867. allwinner,function = "nand0";
  868. allwinner,drive = <0x0>;
  869. allwinner,pull = <0x0>;
  870. linux,phandle = <0x64>;
  871. phandle = <0x64>;
  872. };
  873.  
  874. spi2@0 {
  875. allwinner,pins = "PE1", "PE2", "PE3";
  876. allwinner,function = "spi2";
  877. allwinner,drive = <0x0>;
  878. allwinner,pull = <0x0>;
  879. linux,phandle = <0x65>;
  880. phandle = <0x65>;
  881. };
  882.  
  883. spi2-cs0@0 {
  884. allwinner,pins = "PE0";
  885. allwinner,function = "spi2";
  886. allwinner,drive = <0x0>;
  887. allwinner,pull = <0x0>;
  888. linux,phandle = <0x66>;
  889. phandle = <0x66>;
  890. };
  891.  
  892. uart3@0 {
  893. allwinner,pins = "PG9", "PG10";
  894. allwinner,function = "uart3";
  895. allwinner,drive = <0x0>;
  896. allwinner,pull = <0x0>;
  897. linux,phandle = <0x35>;
  898. phandle = <0x35>;
  899. };
  900.  
  901. uart3-cts-rts@0 {
  902. allwinner,pins = "PG11", "PG12";
  903. allwinner,function = "uart3";
  904. allwinner,drive = <0x0>;
  905. allwinner,pull = <0x0>;
  906. linux,phandle = <0x36>;
  907. phandle = <0x36>;
  908. };
  909.  
  910. pwm0 {
  911. allwinner,pins = "PB2";
  912. allwinner,function = "pwm";
  913. allwinner,drive = <0x0>;
  914. allwinner,pull = <0x0>;
  915. linux,phandle = <0x67>;
  916. phandle = <0x67>;
  917. };
  918.  
  919. lcd_rgb666@0 {
  920. allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", "PD24", "PD25", "PD26", "PD27";
  921. allwinner,function = "lcd0";
  922. allwinner,drive = <0x0>;
  923. allwinner,pull = <0x0>;
  924. linux,phandle = <0x68>;
  925. phandle = <0x68>;
  926. };
  927.  
  928. uart1@0 {
  929. allwinner,pins = "PE10", "PE11";
  930. allwinner,function = "uart1";
  931. allwinner,drive = <0x0>;
  932. allwinner,pull = <0x0>;
  933. linux,phandle = <0x69>;
  934. phandle = <0x69>;
  935. };
  936.  
  937. uart1@1 {
  938. allwinner,pins = "PG3", "PG4";
  939. allwinner,function = "uart1";
  940. allwinner,drive = <0x0>;
  941. allwinner,pull = <0x0>;
  942. linux,phandle = <0x34>;
  943. phandle = <0x34>;
  944. };
  945.  
  946. ahci_pwr_pin@0 {
  947. allwinner,pins = "PB8";
  948. allwinner,function = "gpio_out";
  949. allwinner,drive = <0x0>;
  950. allwinner,pull = <0x0>;
  951. linux,phandle = <0x46>;
  952. phandle = <0x46>;
  953. };
  954.  
  955. usb0_vbus_pin@0 {
  956. allwinner,pins = "PB9";
  957. allwinner,function = "gpio_out";
  958. allwinner,drive = <0x0>;
  959. allwinner,pull = <0x0>;
  960. linux,phandle = <0x6a>;
  961. phandle = <0x6a>;
  962. };
  963.  
  964. usb1_vbus_pin@0 {
  965. allwinner,pins = "PH6";
  966. allwinner,function = "gpio_out";
  967. allwinner,drive = <0x0>;
  968. allwinner,pull = <0x0>;
  969. linux,phandle = <0x48>;
  970. phandle = <0x48>;
  971. };
  972.  
  973. usb2_vbus_pin@0 {
  974. allwinner,pins = "PH3";
  975. allwinner,function = "gpio_out";
  976. allwinner,drive = <0x0>;
  977. allwinner,pull = <0x0>;
  978. linux,phandle = <0x49>;
  979. phandle = <0x49>;
  980. };
  981.  
  982. chip_vbus_pin@0 {
  983. allwinner,pins = "PB10";
  984. allwinner,function = "gpio_out";
  985. allwinner,drive = <0x0>;
  986. allwinner,pull = <0x0>;
  987. linux,phandle = <0x47>;
  988. phandle = <0x47>;
  989. };
  990.  
  991. chip_wifi_reg_on_pin@0 {
  992. allwinner,pins = "PC19";
  993. allwinner,function = "gpio_out";
  994. allwinner,drive = <0x0>;
  995. allwinner,pull = <0x0>;
  996. linux,phandle = <0x4b>;
  997. phandle = <0x4b>;
  998. };
  999.  
  1000. chip_id_det_pin@0 {
  1001. allwinner,pins = "PG2";
  1002. allwinner,function = "gpio_in";
  1003. allwinner,drive = <0x0>;
  1004. allwinner,pull = <0x0>;
  1005. linux,phandle = <0x2a>;
  1006. phandle = <0x2a>;
  1007. };
  1008.  
  1009. chip_w1_pin@0 {
  1010. allwinner,pins = "PD2";
  1011. allwinner,function = "gpio_in";
  1012. allwinner,drive = <0x0>;
  1013. allwinner,pull = <0x1>;
  1014. linux,phandle = <0x4c>;
  1015. phandle = <0x4c>;
  1016. };
  1017. };
  1018.  
  1019. timer@01c20c00 {
  1020. compatible = "allwinner,sun4i-a10-timer";
  1021. reg = <0x1c20c00 0x90>;
  1022. interrupts = <0x16>;
  1023. clocks = <0x9>;
  1024. };
  1025.  
  1026. watchdog@01c20c90 {
  1027. compatible = "allwinner,sun4i-a10-wdt";
  1028. reg = <0x1c20c90 0x10>;
  1029. linux,phandle = <0x6b>;
  1030. phandle = <0x6b>;
  1031. };
  1032.  
  1033. lradc@01c22800 {
  1034. #io-channel-cells = <0x1>;
  1035. compatible = "allwinner,sun4i-a10-lradc";
  1036. reg = <0x1c22800 0x100>;
  1037. interrupts = <0x1f>;
  1038. status = "okay";
  1039. vref-supply = <0x31>;
  1040. linux,phandle = <0x6c>;
  1041. phandle = <0x6c>;
  1042. };
  1043.  
  1044. codec@01c22c00 {
  1045. #sound-dai-cells = <0x0>;
  1046. compatible = "allwinner,sun4i-a10-codec";
  1047. reg = <0x1c22c00 0x40>;
  1048. interrupts = <0x1e>;
  1049. clocks = <0x30 0x0 0x32>;
  1050. clock-names = "apb", "codec";
  1051. dmas = <0x1e 0x0 0x13 0x1e 0x0 0x13>;
  1052. dma-names = "rx", "tx";
  1053. status = "okay";
  1054. linux,phandle = <0x6d>;
  1055. phandle = <0x6d>;
  1056. };
  1057.  
  1058. eeprom@01c23800 {
  1059. compatible = "allwinner,sun4i-a10-sid";
  1060. reg = <0x1c23800 0x10>;
  1061. linux,phandle = <0x6e>;
  1062. phandle = <0x6e>;
  1063. };
  1064.  
  1065. rtp@01c25000 {
  1066. compatible = "allwinner,sun5i-a13-ts";
  1067. reg = <0x1c25000 0x100>;
  1068. interrupts = <0x1d>;
  1069. #thermal-sensor-cells = <0x0>;
  1070. linux,phandle = <0x42>;
  1071. phandle = <0x42>;
  1072. };
  1073.  
  1074. serial@01c28400 {
  1075. compatible = "snps,dw-apb-uart";
  1076. reg = <0x1c28400 0x400>;
  1077. interrupts = <0x2>;
  1078. reg-shift = <0x2>;
  1079. reg-io-width = <0x4>;
  1080. clocks = <0x33 0x11>;
  1081. status = "okay";
  1082. pinctrl-names = "default";
  1083. pinctrl-0 = <0x34>;
  1084. linux,phandle = <0x6f>;
  1085. phandle = <0x6f>;
  1086. };
  1087.  
  1088. serial@01c28c00 {
  1089. compatible = "snps,dw-apb-uart";
  1090. reg = <0x1c28c00 0x400>;
  1091. interrupts = <0x4>;
  1092. reg-shift = <0x2>;
  1093. reg-io-width = <0x4>;
  1094. clocks = <0x33 0x13>;
  1095. status = "okay";
  1096. pinctrl-names = "default";
  1097. pinctrl-0 = <0x35 0x36>;
  1098. linux,phandle = <0x70>;
  1099. phandle = <0x70>;
  1100. };
  1101.  
  1102. i2c@01c2ac00 {
  1103. compatible = "allwinner,sun4i-a10-i2c";
  1104. reg = <0x1c2ac00 0x400>;
  1105. interrupts = <0x7>;
  1106. clocks = <0x33 0x0>;
  1107. status = "okay";
  1108. #address-cells = <0x1>;
  1109. #size-cells = <0x0>;
  1110. pinctrl-names = "default";
  1111. pinctrl-0 = <0x37>;
  1112. linux,phandle = <0x71>;
  1113. phandle = <0x71>;
  1114.  
  1115. pmic@34 {
  1116. reg = <0x34>;
  1117. interrupts = <0x0>;
  1118. compatible = "x-powers,axp209";
  1119. interrupt-controller;
  1120. #interrupt-cells = <0x1>;
  1121. linux,phandle = <0x72>;
  1122. phandle = <0x72>;
  1123.  
  1124. gpio {
  1125. compatible = "x-powers,axp209-gpio";
  1126. gpio-controller;
  1127. #gpio-cells = <0x2>;
  1128. linux,phandle = <0x4a>;
  1129. phandle = <0x4a>;
  1130. };
  1131.  
  1132. regulators {
  1133. x-powers,dcdc-freq = <0x5dc>;
  1134.  
  1135. dcdc2 {
  1136. regulator-name = "cpuvdd";
  1137. regulator-min-microvolt = <0xf4240>;
  1138. regulator-max-microvolt = <0x155cc0>;
  1139. regulator-always-on;
  1140. linux,phandle = <0x8>;
  1141. phandle = <0x8>;
  1142. };
  1143.  
  1144. dcdc3 {
  1145. regulator-name = "corevdd";
  1146. regulator-min-microvolt = <0xf4240>;
  1147. regulator-max-microvolt = <0x13d620>;
  1148. regulator-always-on;
  1149. linux,phandle = <0x73>;
  1150. phandle = <0x73>;
  1151. };
  1152.  
  1153. ldo1 {
  1154. regulator-always-on;
  1155. regulator-min-microvolt = <0x13d620>;
  1156. regulator-max-microvolt = <0x13d620>;
  1157. regulator-name = "rtcvdd";
  1158. linux,phandle = <0x74>;
  1159. phandle = <0x74>;
  1160. };
  1161.  
  1162. ldo2 {
  1163. regulator-name = "avcc";
  1164. regulator-min-microvolt = <0x2932e0>;
  1165. regulator-max-microvolt = <0x325aa0>;
  1166. regulator-always-on;
  1167. linux,phandle = <0x75>;
  1168. phandle = <0x75>;
  1169. };
  1170.  
  1171. ldo3 {
  1172. regulator-name = "vcc-wifi-1";
  1173. regulator-min-microvolt = <0x325aa0>;
  1174. regulator-max-microvolt = <0x325aa0>;
  1175. linux,phandle = <0x4d>;
  1176. phandle = <0x4d>;
  1177. };
  1178.  
  1179. ldo4 {
  1180. regulator-name = "vcc-wifi-2";
  1181. regulator-min-microvolt = <0x325aa0>;
  1182. regulator-max-microvolt = <0x325aa0>;
  1183. linux,phandle = <0x4e>;
  1184. phandle = <0x4e>;
  1185. };
  1186.  
  1187. ldo5 {
  1188. regulator-name = "vcc-1v8";
  1189. regulator-min-microvolt = <0x1b7740>;
  1190. regulator-max-microvolt = <0x1b7740>;
  1191. linux,phandle = <0x76>;
  1192. phandle = <0x76>;
  1193. };
  1194. };
  1195.  
  1196. usb_power_supply {
  1197. compatible = "x-powers,axp202-usb-power-supply";
  1198. status = "okay";
  1199. linux,phandle = <0x2c>;
  1200. phandle = <0x2c>;
  1201. };
  1202. };
  1203. };
  1204.  
  1205. i2c@01c2b000 {
  1206. compatible = "allwinner,sun4i-a10-i2c";
  1207. reg = <0x1c2b000 0x400>;
  1208. interrupts = <0x8>;
  1209. clocks = <0x33 0x1>;
  1210. status = "okay";
  1211. #address-cells = <0x1>;
  1212. #size-cells = <0x0>;
  1213. pinctrl-names = "default";
  1214. pinctrl-0 = <0x38>;
  1215. linux,phandle = <0x77>;
  1216. phandle = <0x77>;
  1217. };
  1218.  
  1219. i2c@01c2b400 {
  1220. compatible = "allwinner,sun4i-a10-i2c";
  1221. reg = <0x1c2b400 0x400>;
  1222. interrupts = <0x9>;
  1223. clocks = <0x33 0x2>;
  1224. status = "okay";
  1225. #address-cells = <0x1>;
  1226. #size-cells = <0x0>;
  1227. pinctrl-names = "default";
  1228. pinctrl-0 = <0x39>;
  1229. linux,phandle = <0x78>;
  1230. phandle = <0x78>;
  1231.  
  1232. gpio@38 {
  1233. compatible = "nxp,pcf8574a";
  1234. reg = <0x38>;
  1235. gpio-controller;
  1236. #gpio-cells = <0x2>;
  1237. interrupt-parent = <0x2b>;
  1238. interrupts = <0x6 0x0 0x2>;
  1239. interrupt-controller;
  1240. #interrupt-cells = <0x2>;
  1241. linux,phandle = <0x79>;
  1242. phandle = <0x79>;
  1243. };
  1244. };
  1245.  
  1246. timer@01c60000 {
  1247. compatible = "allwinner,sun5i-a13-hstimer";
  1248. reg = <0x1c60000 0x1000>;
  1249. interrupts = <0x52 0x53>;
  1250. clocks = <0x2 0x1c>;
  1251. };
  1252.  
  1253. lcd-controller@01c0c000 {
  1254. compatible = "allwinner,sun5i-a13-tcon";
  1255. reg = <0x1c0c000 0x1000>;
  1256. interrupts = <0x2c>;
  1257. resets = <0x4 0x1>;
  1258. reset-names = "lcd";
  1259. clocks = <0x2 0x24 0x4 0x6>;
  1260. clock-names = "ahb", "tcon-ch0", "tcon-ch1";
  1261. clock-output-names = "tcon-pixel-clock";
  1262. status = "okay";
  1263. linux,phandle = <0x7a>;
  1264. phandle = <0x7a>;
  1265.  
  1266. ports {
  1267. #address-cells = <0x1>;
  1268. #size-cells = <0x0>;
  1269.  
  1270. port@0 {
  1271. #address-cells = <0x1>;
  1272. #size-cells = <0x0>;
  1273. reg = <0x0>;
  1274. linux,phandle = <0x7b>;
  1275. phandle = <0x7b>;
  1276.  
  1277. endpoint@0 {
  1278. reg = <0x0>;
  1279. remote-endpoint = <0x3a>;
  1280. linux,phandle = <0x3f>;
  1281. phandle = <0x3f>;
  1282. };
  1283. };
  1284.  
  1285. port@1 {
  1286. #address-cells = <0x1>;
  1287. #size-cells = <0x0>;
  1288. reg = <0x1>;
  1289. linux,phandle = <0x7c>;
  1290. phandle = <0x7c>;
  1291.  
  1292. endpoint@1 {
  1293. reg = <0x1>;
  1294. remote-endpoint = <0x3b>;
  1295. linux,phandle = <0x40>;
  1296. phandle = <0x40>;
  1297. };
  1298. };
  1299. };
  1300. };
  1301.  
  1302. pwm@01c20e00 {
  1303. compatible = "allwinner,sun5i-a13-pwm";
  1304. reg = <0x1c20e00 0xc>;
  1305. clocks = <0x9>;
  1306. #pwm-cells = <0x3>;
  1307. status = "disabled";
  1308. linux,phandle = <0x7d>;
  1309. phandle = <0x7d>;
  1310. };
  1311.  
  1312. display-frontend@01e00000 {
  1313. compatible = "allwinner,sun5i-a13-display-frontend";
  1314. reg = <0x1e00000 0x20000>;
  1315. interrupts = <0x2f>;
  1316. clocks = <0x2 0x2e 0x3c 0x5 0x19>;
  1317. clock-names = "ahb", "mod", "ram";
  1318. resets = <0x3c>;
  1319. status = "disabled";
  1320. linux,phandle = <0x45>;
  1321. phandle = <0x45>;
  1322.  
  1323. ports {
  1324. #address-cells = <0x1>;
  1325. #size-cells = <0x0>;
  1326.  
  1327. port@1 {
  1328. #address-cells = <0x1>;
  1329. #size-cells = <0x0>;
  1330. reg = <0x1>;
  1331. linux,phandle = <0x7e>;
  1332. phandle = <0x7e>;
  1333.  
  1334. endpoint@0 {
  1335. reg = <0x0>;
  1336. remote-endpoint = <0x3d>;
  1337. linux,phandle = <0x3e>;
  1338. phandle = <0x3e>;
  1339. };
  1340. };
  1341. };
  1342. };
  1343.  
  1344. display-backend@01e60000 {
  1345. compatible = "allwinner,sun5i-a13-display-backend";
  1346. reg = <0x1e60000 0x10000>;
  1347. clocks = <0x2 0x2c 0x3 0x5 0x1a>;
  1348. clock-names = "ahb", "mod", "ram";
  1349. resets = <0x3>;
  1350. status = "okay";
  1351. assigned-clocks = <0x3>;
  1352. assigned-clock-rates = <0x11e1a300>;
  1353. linux,phandle = <0x7f>;
  1354. phandle = <0x7f>;
  1355.  
  1356. ports {
  1357. #address-cells = <0x1>;
  1358. #size-cells = <0x0>;
  1359.  
  1360. port@0 {
  1361. #address-cells = <0x1>;
  1362. #size-cells = <0x0>;
  1363. reg = <0x0>;
  1364. linux,phandle = <0x80>;
  1365. phandle = <0x80>;
  1366.  
  1367. endpoint@0 {
  1368. reg = <0x0>;
  1369. remote-endpoint = <0x3e>;
  1370. linux,phandle = <0x3d>;
  1371. phandle = <0x3d>;
  1372. };
  1373. };
  1374.  
  1375. port@1 {
  1376. #address-cells = <0x1>;
  1377. #size-cells = <0x0>;
  1378. reg = <0x1>;
  1379. linux,phandle = <0x81>;
  1380. phandle = <0x81>;
  1381.  
  1382. endpoint@0 {
  1383. reg = <0x0>;
  1384. remote-endpoint = <0x3f>;
  1385. linux,phandle = <0x3a>;
  1386. phandle = <0x3a>;
  1387. };
  1388. };
  1389. };
  1390. };
  1391.  
  1392. tv-encoder@01c0a000 {
  1393. compatible = "allwinner,sun4i-a10-tv-encoder";
  1394. reg = <0x1c0a000 0x1000>;
  1395. clocks = <0x2 0x22>;
  1396. resets = <0x4 0x0>;
  1397. status = "okay";
  1398. linux,phandle = <0x82>;
  1399. phandle = <0x82>;
  1400.  
  1401. port {
  1402. #address-cells = <0x1>;
  1403. #size-cells = <0x0>;
  1404.  
  1405. endpoint@0 {
  1406. reg = <0x0>;
  1407. remote-endpoint = <0x40>;
  1408. linux,phandle = <0x3b>;
  1409. phandle = <0x3b>;
  1410. };
  1411. };
  1412. };
  1413.  
  1414. gpu@01c40000 {
  1415. compatible = "arm,mali-400", "arm,mali-utgard";
  1416. reg = <0x1c40000 0x10000>;
  1417. interrupts = <0x45 0x46 0x47 0x48 0x49>;
  1418. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPMU";
  1419. clocks = <0x2 0x34 0x41>;
  1420. clock-names = "ahb", "mod";
  1421. resets = <0x41>;
  1422. assigned-clocks = <0x41>;
  1423. assigned-clock-rates = <0x1298be00>;
  1424. linux,phandle = <0x83>;
  1425. phandle = <0x83>;
  1426. };
  1427. };
  1428.  
  1429. thermal-zones {
  1430.  
  1431. cpu_thermal {
  1432. polling-delay-passive = <0xfa>;
  1433. polling-delay = <0x3e8>;
  1434. thermal-sensors = <0x42>;
  1435.  
  1436. cooling-maps {
  1437.  
  1438. map0 {
  1439. trip = <0x43>;
  1440. cooling-device = <0x44 0xffffffff 0xffffffff>;
  1441. };
  1442. };
  1443.  
  1444. trips {
  1445.  
  1446. cpu_alert0 {
  1447. temperature = <0x14c08>;
  1448. hysteresis = <0x7d0>;
  1449. type = "passive";
  1450. linux,phandle = <0x43>;
  1451. phandle = <0x43>;
  1452. };
  1453.  
  1454. cpu_crit {
  1455. temperature = <0x186a0>;
  1456. hysteresis = <0x7d0>;
  1457. type = "critical";
  1458. linux,phandle = <0x84>;
  1459. phandle = <0x84>;
  1460. };
  1461. };
  1462. };
  1463. };
  1464.  
  1465. display-engine {
  1466. compatible = "allwinner,sun5i-a13-display-engine";
  1467. allwinner,pipelines = <0x45>;
  1468. };
  1469.  
  1470. ahci-5v {
  1471. compatible = "regulator-fixed";
  1472. pinctrl-names = "default";
  1473. pinctrl-0 = <0x46>;
  1474. regulator-name = "ahci-5v";
  1475. regulator-min-microvolt = <0x4c4b40>;
  1476. regulator-max-microvolt = <0x4c4b40>;
  1477. regulator-boot-on;
  1478. enable-active-high;
  1479. gpio = <0x2b 0x1 0x8 0x0>;
  1480. status = "disabled";
  1481. linux,phandle = <0x85>;
  1482. phandle = <0x85>;
  1483. };
  1484.  
  1485. usb0-vbus {
  1486. compatible = "regulator-fixed";
  1487. pinctrl-names = "default";
  1488. pinctrl-0 = <0x47>;
  1489. regulator-name = "usb0-vbus";
  1490. regulator-min-microvolt = <0x4c4b40>;
  1491. regulator-max-microvolt = <0x4c4b40>;
  1492. enable-active-high;
  1493. gpio = <0x2b 0x1 0xa 0x0>;
  1494. status = "okay";
  1495. vin-supply = <0x2e>;
  1496. linux,phandle = <0x2d>;
  1497. phandle = <0x2d>;
  1498. };
  1499.  
  1500. usb1-vbus {
  1501. compatible = "regulator-fixed";
  1502. pinctrl-names = "default";
  1503. pinctrl-0 = <0x48>;
  1504. regulator-name = "usb1-vbus";
  1505. regulator-min-microvolt = <0x4c4b40>;
  1506. regulator-max-microvolt = <0x4c4b40>;
  1507. regulator-boot-on;
  1508. enable-active-high;
  1509. gpio = <0x2b 0x7 0x6 0x0>;
  1510. status = "disabled";
  1511. linux,phandle = <0x86>;
  1512. phandle = <0x86>;
  1513. };
  1514.  
  1515. usb2-vbus {
  1516. compatible = "regulator-fixed";
  1517. pinctrl-names = "default";
  1518. pinctrl-0 = <0x49>;
  1519. regulator-name = "usb2-vbus";
  1520. regulator-min-microvolt = <0x4c4b40>;
  1521. regulator-max-microvolt = <0x4c4b40>;
  1522. regulator-boot-on;
  1523. enable-active-high;
  1524. gpio = <0x2b 0x7 0x3 0x0>;
  1525. status = "disabled";
  1526. linux,phandle = <0x87>;
  1527. phandle = <0x87>;
  1528. };
  1529.  
  1530. vcc3v0 {
  1531. compatible = "regulator-fixed";
  1532. regulator-name = "vcc3v0";
  1533. regulator-min-microvolt = <0x2dc6c0>;
  1534. regulator-max-microvolt = <0x2dc6c0>;
  1535. linux,phandle = <0x31>;
  1536. phandle = <0x31>;
  1537. };
  1538.  
  1539. vcc3v3 {
  1540. compatible = "regulator-fixed";
  1541. regulator-name = "vcc3v3";
  1542. regulator-min-microvolt = <0x325aa0>;
  1543. regulator-max-microvolt = <0x325aa0>;
  1544. linux,phandle = <0x88>;
  1545. phandle = <0x88>;
  1546. };
  1547.  
  1548. vcc5v0 {
  1549. compatible = "regulator-fixed";
  1550. regulator-name = "vcc5v0";
  1551. regulator-min-microvolt = <0x4c4b40>;
  1552. regulator-max-microvolt = <0x4c4b40>;
  1553. linux,phandle = <0x2e>;
  1554. phandle = <0x2e>;
  1555. };
  1556.  
  1557. leds {
  1558. compatible = "gpio-leds";
  1559.  
  1560. status {
  1561. label = "chip:white:status";
  1562. gpios = <0x4a 0x2 0x0>;
  1563. default-state = "on";
  1564. linux,default-trigger = "heartbeat";
  1565. linux,phandle = <0x89>;
  1566. phandle = <0x89>;
  1567. };
  1568. };
  1569.  
  1570. mmc0_pwrseq {
  1571. compatible = "mmc-pwrseq-simple";
  1572. pinctrl-names = "default";
  1573. pinctrl-0 = <0x4b>;
  1574. reset-gpios = <0x2b 0x2 0x13 0x1>;
  1575. linux,phandle = <0x24>;
  1576. phandle = <0x24>;
  1577. };
  1578.  
  1579. onewire {
  1580. compatible = "w1-gpio";
  1581. gpios = <0x2b 0x3 0x2 0x0>;
  1582. pinctrl-names = "default";
  1583. pinctrl-0 = <0x4c>;
  1584. };
  1585.  
  1586. wifi_reg {
  1587. compatible = "coupled-voltage-regulator";
  1588. regulator-name = "vcc-wifi";
  1589. vin0-supply = <0x4d>;
  1590. vin1-supply = <0x4e>;
  1591. linux,phandle = <0x23>;
  1592. phandle = <0x23>;
  1593. };
  1594.  
  1595. __symbols__ {
  1596. cpu0 = "/cpus/cpu@0";
  1597. dummy = "/clocks/dummy";
  1598. osc24M = "/clocks/clk@01c20050";
  1599. osc3M = "/clocks/osc3M_clk";
  1600. osc32k = "/clocks/clk@0";
  1601. pll1 = "/clocks/clk@01c20000";
  1602. pll2 = "/clocks/clk@01c20008";
  1603. pll3 = "/clocks/clk@01c20010";
  1604. pll3x2 = "/clocks/pll3x2_clk";
  1605. pll4 = "/clocks/clk@01c20018";
  1606. pll5 = "/clocks/clk@01c20020";
  1607. pll6 = "/clocks/clk@01c20028";
  1608. pll7 = "/clocks/clk@01c20030";
  1609. pll7x2 = "/clocks/pll7x2_clk";
  1610. cpu = "/clocks/cpu@01c20054";
  1611. axi = "/clocks/axi@01c20054";
  1612. ahb = "/clocks/ahb@01c20054";
  1613. apb0 = "/clocks/apb0@01c20054";
  1614. apb1 = "/clocks/clk@01c20058";
  1615. axi_gates = "/clocks/clk@01c2005c";
  1616. nand_clk = "/clocks/clk@01c20080";
  1617. ms_clk = "/clocks/clk@01c20084";
  1618. mmc0_clk = "/clocks/clk@01c20088";
  1619. mmc1_clk = "/clocks/clk@01c2008c";
  1620. mmc2_clk = "/clocks/clk@01c20090";
  1621. ts_clk = "/clocks/clk@01c20098";
  1622. ss_clk = "/clocks/clk@01c2009c";
  1623. spi0_clk = "/clocks/clk@01c200a0";
  1624. spi1_clk = "/clocks/clk@01c200a4";
  1625. spi2_clk = "/clocks/clk@01c200a8";
  1626. ir0_clk = "/clocks/clk@01c200b0";
  1627. usb_clk = "/clocks/clk@01c200cc";
  1628. codec_clk = "/clocks/clk@01c20140";
  1629. mbus_clk = "/clocks/clk@01c2015c";
  1630. ahb_gates = "/clocks/clk@01c20060";
  1631. apb0_gates = "/clocks/clk@01c20068";
  1632. apb1_gates = "/clocks/clk@01c2006c";
  1633. dram_gates = "/clocks/clk@01c20100";
  1634. de_be_clk = "/clocks/clk@01c20104";
  1635. de_fe_clk = "/clocks/clk@01c2010c";
  1636. tcon_ch0_clk = "/clocks/clk@01c20118";
  1637. tcon_ch1_clk = "/clocks/clk@01c2012c";
  1638. mali_clk = "/clocks/clk@01c20154";
  1639. sram_a = "/soc@01c00000/sram-controller@01c00000/sram@00000000";
  1640. sram_d = "/soc@01c00000/sram-controller@01c00000/sram@00010000";
  1641. otg_sram = "/soc@01c00000/sram-controller@01c00000/sram@00010000/sram-section@0000";
  1642. dma = "/soc@01c00000/dma-controller@01c02000";
  1643. nfc = "/soc@01c00000/nand@01c03000";
  1644. spi0 = "/soc@01c00000/spi@01c05000";
  1645. spi1 = "/soc@01c00000/spi@01c06000";
  1646. mmc0 = "/soc@01c00000/mmc@01c0f000";
  1647. mmc1 = "/soc@01c00000/mmc@01c10000";
  1648. mmc2 = "/soc@01c00000/mmc@01c11000";
  1649. usb_otg = "/soc@01c00000/usb@01c13000";
  1650. usbphy = "/soc@01c00000/phy@01c13400";
  1651. ehci0 = "/soc@01c00000/usb@01c14000";
  1652. ohci0 = "/soc@01c00000/usb@01c14400";
  1653. spi2 = "/soc@01c00000/spi@01c17000";
  1654. intc = "/soc@01c00000/interrupt-controller@01c20400";
  1655. pio = "/soc@01c00000/pinctrl@01c20800";
  1656. i2c0_pins_a = "/soc@01c00000/pinctrl@01c20800/i2c0@0";
  1657. i2c1_pins_a = "/soc@01c00000/pinctrl@01c20800/i2c1@0";
  1658. i2c2_pins_a = "/soc@01c00000/pinctrl@01c20800/i2c2@0";
  1659. lcd_rgb565_pins = "/soc@01c00000/pinctrl@01c20800/lcd_rgb565@0";
  1660. mmc0_pins_a = "/soc@01c00000/pinctrl@01c20800/mmc0@0";
  1661. mmc2_pins_a = "/soc@01c00000/pinctrl@01c20800/mmc2@0";
  1662. nand_pins_a = "/soc@01c00000/pinctrl@01c20800/nand_base0@0";
  1663. nand_cs0_pins_a = "/soc@01c00000/pinctrl@01c20800/nand_cs@0";
  1664. nand_cs1_pins_a = "/soc@01c00000/pinctrl@01c20800/nand_cs@1";
  1665. nand_rb0_pins_a = "/soc@01c00000/pinctrl@01c20800/nand_rb@0";
  1666. nand_rb1_pins_a = "/soc@01c00000/pinctrl@01c20800/nand_rb@1";
  1667. spi2_pins_a = "/soc@01c00000/pinctrl@01c20800/spi2@0";
  1668. spi2_cs0_pins_a = "/soc@01c00000/pinctrl@01c20800/spi2-cs0@0";
  1669. uart3_pins_a = "/soc@01c00000/pinctrl@01c20800/uart3@0";
  1670. uart3_pins_cts_rts_a = "/soc@01c00000/pinctrl@01c20800/uart3-cts-rts@0";
  1671. pwm0_pins = "/soc@01c00000/pinctrl@01c20800/pwm0";
  1672. lcd_rgb666_pins = "/soc@01c00000/pinctrl@01c20800/lcd_rgb666@0";
  1673. uart1_pins_a = "/soc@01c00000/pinctrl@01c20800/uart1@0";
  1674. uart1_pins_b = "/soc@01c00000/pinctrl@01c20800/uart1@1";
  1675. ahci_pwr_pin_a = "/soc@01c00000/pinctrl@01c20800/ahci_pwr_pin@0";
  1676. usb0_vbus_pin_a = "/soc@01c00000/pinctrl@01c20800/usb0_vbus_pin@0";
  1677. usb1_vbus_pin_a = "/soc@01c00000/pinctrl@01c20800/usb1_vbus_pin@0";
  1678. usb2_vbus_pin_a = "/soc@01c00000/pinctrl@01c20800/usb2_vbus_pin@0";
  1679. chip_vbus_pin = "/soc@01c00000/pinctrl@01c20800/chip_vbus_pin@0";
  1680. chip_wifi_reg_on_pin = "/soc@01c00000/pinctrl@01c20800/chip_wifi_reg_on_pin@0";
  1681. chip_id_det_pin = "/soc@01c00000/pinctrl@01c20800/chip_id_det_pin@0";
  1682. chip_w1_pin = "/soc@01c00000/pinctrl@01c20800/chip_w1_pin@0";
  1683. wdt = "/soc@01c00000/watchdog@01c20c90";
  1684. lradc = "/soc@01c00000/lradc@01c22800";
  1685. codec = "/soc@01c00000/codec@01c22c00";
  1686. sid = "/soc@01c00000/eeprom@01c23800";
  1687. rtp = "/soc@01c00000/rtp@01c25000";
  1688. uart1 = "/soc@01c00000/serial@01c28400";
  1689. uart3 = "/soc@01c00000/serial@01c28c00";
  1690. i2c0 = "/soc@01c00000/i2c@01c2ac00";
  1691. axp209 = "/soc@01c00000/i2c@01c2ac00/pmic@34";
  1692. axp_gpio = "/soc@01c00000/i2c@01c2ac00/pmic@34/gpio";
  1693. reg_dcdc2 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/dcdc2";
  1694. reg_dcdc3 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/dcdc3";
  1695. reg_ldo1 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/ldo1";
  1696. reg_ldo2 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/ldo2";
  1697. reg_ldo3 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/ldo3";
  1698. reg_ldo4 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/ldo4";
  1699. reg_ldo5 = "/soc@01c00000/i2c@01c2ac00/pmic@34/regulators/ldo5";
  1700. usb_power_supply = "/soc@01c00000/i2c@01c2ac00/pmic@34/usb_power_supply";
  1701. i2c1 = "/soc@01c00000/i2c@01c2b000";
  1702. i2c2 = "/soc@01c00000/i2c@01c2b400";
  1703. xio = "/soc@01c00000/i2c@01c2b400/gpio@38";
  1704. tcon0 = "/soc@01c00000/lcd-controller@01c0c000";
  1705. tcon0_in = "/soc@01c00000/lcd-controller@01c0c000/ports/port@0";
  1706. tcon0_in_be0 = "/soc@01c00000/lcd-controller@01c0c000/ports/port@0/endpoint@0";
  1707. tcon0_out = "/soc@01c00000/lcd-controller@01c0c000/ports/port@1";
  1708. tcon0_out_tve0 = "/soc@01c00000/lcd-controller@01c0c000/ports/port@1/endpoint@1";
  1709. pwm = "/soc@01c00000/pwm@01c20e00";
  1710. fe0 = "/soc@01c00000/display-frontend@01e00000";
  1711. fe0_out = "/soc@01c00000/display-frontend@01e00000/ports/port@1";
  1712. fe0_out_be0 = "/soc@01c00000/display-frontend@01e00000/ports/port@1/endpoint@0";
  1713. be0 = "/soc@01c00000/display-backend@01e60000";
  1714. be0_in = "/soc@01c00000/display-backend@01e60000/ports/port@0";
  1715. be0_in_fe0 = "/soc@01c00000/display-backend@01e60000/ports/port@0/endpoint@0";
  1716. be0_out = "/soc@01c00000/display-backend@01e60000/ports/port@1";
  1717. be0_out_tcon0 = "/soc@01c00000/display-backend@01e60000/ports/port@1/endpoint@0";
  1718. tve0 = "/soc@01c00000/tv-encoder@01c0a000";
  1719. tve0_in_tcon0 = "/soc@01c00000/tv-encoder@01c0a000/port/endpoint@0";
  1720. mali = "/soc@01c00000/gpu@01c40000";
  1721. cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert0";
  1722. cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
  1723. reg_ahci_5v = "/ahci-5v";
  1724. reg_usb0_vbus = "/usb0-vbus";
  1725. reg_usb1_vbus = "/usb1-vbus";
  1726. reg_usb2_vbus = "/usb2-vbus";
  1727. reg_vcc3v0 = "/vcc3v0";
  1728. reg_vcc3v3 = "/vcc3v3";
  1729. reg_vcc5v0 = "/vcc5v0";
  1730. leds_status = "/leds/status";
  1731. mmc0_pwrseq = "/mmc0_pwrseq";
  1732. vcc_wifi = "/wifi_reg";
  1733. };
  1734.  
  1735. __local_fixups__ {
  1736. interrupt-parent = <0x0>;
  1737.  
  1738. chosen {
  1739.  
  1740. framebuffer@0 {
  1741. clocks = <0x0 0x8 0x10 0x14 0x18>;
  1742. };
  1743.  
  1744. framebuffer@1 {
  1745. clocks = <0x0 0x8 0x10 0x18 0x1c 0x20>;
  1746. };
  1747. };
  1748.  
  1749. cpus {
  1750.  
  1751. cpu@0 {
  1752. clocks = <0x0>;
  1753. cpu-supply = <0x0>;
  1754. };
  1755. };
  1756.  
  1757. clocks {
  1758.  
  1759. osc3M_clk {
  1760. clocks = <0x0>;
  1761. };
  1762.  
  1763. clk@01c20000 {
  1764. clocks = <0x0>;
  1765. };
  1766.  
  1767. clk@01c20008 {
  1768. clocks = <0x0>;
  1769. };
  1770.  
  1771. clk@01c20010 {
  1772. clocks = <0x0>;
  1773. };
  1774.  
  1775. pll3x2_clk {
  1776. clocks = <0x0>;
  1777. };
  1778.  
  1779. clk@01c20018 {
  1780. clocks = <0x0>;
  1781. };
  1782.  
  1783. clk@01c20020 {
  1784. clocks = <0x0>;
  1785. };
  1786.  
  1787. clk@01c20028 {
  1788. clocks = <0x0>;
  1789. };
  1790.  
  1791. clk@01c20030 {
  1792. clocks = <0x0>;
  1793. };
  1794.  
  1795. pll7x2_clk {
  1796. clocks = <0x0>;
  1797. };
  1798.  
  1799. cpu@01c20054 {
  1800. clocks = <0x0 0x4 0x8 0xc>;
  1801. };
  1802.  
  1803. axi@01c20054 {
  1804. clocks = <0x0>;
  1805. };
  1806.  
  1807. ahb@01c20054 {
  1808. clocks = <0x0 0x4 0x8>;
  1809. assigned-clocks = <0x0>;
  1810. assigned-clock-parents = <0x0>;
  1811. };
  1812.  
  1813. apb0@01c20054 {
  1814. clocks = <0x0>;
  1815. };
  1816.  
  1817. clk@01c20058 {
  1818. clocks = <0x0 0x4 0xc>;
  1819. };
  1820.  
  1821. clk@01c2005c {
  1822. clocks = <0x0>;
  1823. };
  1824.  
  1825. clk@01c20080 {
  1826. clocks = <0x0 0x4 0xc>;
  1827. };
  1828.  
  1829. clk@01c20084 {
  1830. clocks = <0x0 0x4 0xc>;
  1831. };
  1832.  
  1833. clk@01c20088 {
  1834. clocks = <0x0 0x4 0xc>;
  1835. };
  1836.  
  1837. clk@01c2008c {
  1838. clocks = <0x0 0x4 0xc>;
  1839. };
  1840.  
  1841. clk@01c20090 {
  1842. clocks = <0x0 0x4 0xc>;
  1843. };
  1844.  
  1845. clk@01c20098 {
  1846. clocks = <0x0 0x4 0xc>;
  1847. };
  1848.  
  1849. clk@01c2009c {
  1850. clocks = <0x0 0x4 0xc>;
  1851. };
  1852.  
  1853. clk@01c200a0 {
  1854. clocks = <0x0 0x4 0xc>;
  1855. };
  1856.  
  1857. clk@01c200a4 {
  1858. clocks = <0x0 0x4 0xc>;
  1859. };
  1860.  
  1861. clk@01c200a8 {
  1862. clocks = <0x0 0x4 0xc>;
  1863. };
  1864.  
  1865. clk@01c200b0 {
  1866. clocks = <0x0 0x4 0xc>;
  1867. };
  1868.  
  1869. clk@01c200cc {
  1870. clocks = <0x0>;
  1871. };
  1872.  
  1873. clk@01c20140 {
  1874. clocks = <0x0>;
  1875. };
  1876.  
  1877. clk@01c2015c {
  1878. clocks = <0x0 0x4 0xc>;
  1879. };
  1880.  
  1881. clk@01c20060 {
  1882. clocks = <0x0>;
  1883. };
  1884.  
  1885. clk@01c20068 {
  1886. clocks = <0x0>;
  1887. };
  1888.  
  1889. clk@01c2006c {
  1890. clocks = <0x0>;
  1891. };
  1892.  
  1893. clk@01c20100 {
  1894. clocks = <0x0>;
  1895. };
  1896.  
  1897. clk@01c20104 {
  1898. clocks = <0x0 0x4 0x8>;
  1899. };
  1900.  
  1901. clk@01c2010c {
  1902. clocks = <0x0 0x4 0x8>;
  1903. };
  1904.  
  1905. clk@01c20118 {
  1906. clocks = <0x0 0x4 0x8 0xc>;
  1907. };
  1908.  
  1909. clk@01c2012c {
  1910. clocks = <0x0 0x4 0x8 0xc>;
  1911. };
  1912.  
  1913. clk@01c20154 {
  1914. clocks = <0x0 0x4 0x8 0x10 0x14>;
  1915. };
  1916. };
  1917.  
  1918. soc@01c00000 {
  1919.  
  1920. dma-controller@01c02000 {
  1921. clocks = <0x0>;
  1922. };
  1923.  
  1924. nand@01c03000 {
  1925. clocks = <0x0 0x8>;
  1926. pinctrl-0 = <0x0 0x4 0x8>;
  1927. dmas = <0x0>;
  1928. };
  1929.  
  1930. spi@01c05000 {
  1931. clocks = <0x0 0x8>;
  1932. dmas = <0x0 0xc>;
  1933. };
  1934.  
  1935. spi@01c06000 {
  1936. clocks = <0x0 0x8>;
  1937. dmas = <0x0 0xc>;
  1938. };
  1939.  
  1940. mmc@01c0f000 {
  1941. clocks = <0x0 0x8 0x10 0x18>;
  1942. pinctrl-0 = <0x0>;
  1943. vmmc-supply = <0x0>;
  1944. mmc-pwrseq = <0x0>;
  1945. };
  1946.  
  1947. mmc@01c10000 {
  1948. clocks = <0x0 0x8 0x10 0x18>;
  1949. };
  1950.  
  1951. mmc@01c11000 {
  1952. clocks = <0x0 0x8 0x10 0x18>;
  1953. };
  1954.  
  1955. usb@01c13000 {
  1956. clocks = <0x0>;
  1957. phys = <0x0>;
  1958. extcon = <0x0>;
  1959. allwinner,sram = <0x0>;
  1960. };
  1961.  
  1962. phy@01c13400 {
  1963. clocks = <0x0>;
  1964. resets = <0x0 0x8>;
  1965. pinctrl-0 = <0x0>;
  1966. usb0_id_det-gpio = <0x0>;
  1967. usb0_vbus_power-supply = <0x0>;
  1968. usb0_vbus-supply = <0x0>;
  1969. usb1_vbus-supply = <0x0>;
  1970. };
  1971.  
  1972. usb@01c14000 {
  1973. clocks = <0x0>;
  1974. phys = <0x0>;
  1975. };
  1976.  
  1977. usb@01c14400 {
  1978. clocks = <0x0 0x8>;
  1979. phys = <0x0>;
  1980. };
  1981.  
  1982. spi@01c17000 {
  1983. clocks = <0x0 0x8>;
  1984. dmas = <0x0 0xc>;
  1985. };
  1986.  
  1987. pinctrl@01c20800 {
  1988. clocks = <0x0>;
  1989. };
  1990.  
  1991. timer@01c20c00 {
  1992. clocks = <0x0>;
  1993. };
  1994.  
  1995. lradc@01c22800 {
  1996. vref-supply = <0x0>;
  1997. };
  1998.  
  1999. codec@01c22c00 {
  2000. clocks = <0x0 0x8>;
  2001. dmas = <0x0 0xc>;
  2002. };
  2003.  
  2004. serial@01c28400 {
  2005. clocks = <0x0>;
  2006. pinctrl-0 = <0x0>;
  2007. };
  2008.  
  2009. serial@01c28c00 {
  2010. clocks = <0x0>;
  2011. pinctrl-0 = <0x0 0x4>;
  2012. };
  2013.  
  2014. i2c@01c2ac00 {
  2015. clocks = <0x0>;
  2016. pinctrl-0 = <0x0>;
  2017. };
  2018.  
  2019. i2c@01c2b000 {
  2020. clocks = <0x0>;
  2021. pinctrl-0 = <0x0>;
  2022. };
  2023.  
  2024. i2c@01c2b400 {
  2025. clocks = <0x0>;
  2026. pinctrl-0 = <0x0>;
  2027.  
  2028. gpio@38 {
  2029. interrupt-parent = <0x0>;
  2030. };
  2031. };
  2032.  
  2033. timer@01c60000 {
  2034. clocks = <0x0>;
  2035. };
  2036.  
  2037. lcd-controller@01c0c000 {
  2038. resets = <0x0>;
  2039. clocks = <0x0 0x8 0xc>;
  2040.  
  2041. ports {
  2042.  
  2043. port@0 {
  2044.  
  2045. endpoint@0 {
  2046. remote-endpoint = <0x0>;
  2047. };
  2048. };
  2049.  
  2050. port@1 {
  2051.  
  2052. endpoint@1 {
  2053. remote-endpoint = <0x0>;
  2054. };
  2055. };
  2056. };
  2057. };
  2058.  
  2059. pwm@01c20e00 {
  2060. clocks = <0x0>;
  2061. };
  2062.  
  2063. display-frontend@01e00000 {
  2064. clocks = <0x0 0x8 0xc>;
  2065. resets = <0x0>;
  2066.  
  2067. ports {
  2068.  
  2069. port@1 {
  2070.  
  2071. endpoint@0 {
  2072. remote-endpoint = <0x0>;
  2073. };
  2074. };
  2075. };
  2076. };
  2077.  
  2078. display-backend@01e60000 {
  2079. clocks = <0x0 0x8 0xc>;
  2080. resets = <0x0>;
  2081. assigned-clocks = <0x0>;
  2082.  
  2083. ports {
  2084.  
  2085. port@0 {
  2086.  
  2087. endpoint@0 {
  2088. remote-endpoint = <0x0>;
  2089. };
  2090. };
  2091.  
  2092. port@1 {
  2093.  
  2094. endpoint@0 {
  2095. remote-endpoint = <0x0>;
  2096. };
  2097. };
  2098. };
  2099. };
  2100.  
  2101. tv-encoder@01c0a000 {
  2102. clocks = <0x0>;
  2103. resets = <0x0>;
  2104.  
  2105. port {
  2106.  
  2107. endpoint@0 {
  2108. remote-endpoint = <0x0>;
  2109. };
  2110. };
  2111. };
  2112.  
  2113. gpu@01c40000 {
  2114. clocks = <0x0 0x8>;
  2115. resets = <0x0>;
  2116. assigned-clocks = <0x0>;
  2117. };
  2118. };
  2119.  
  2120. thermal-zones {
  2121.  
  2122. cpu_thermal {
  2123. thermal-sensors = <0x0>;
  2124.  
  2125. cooling-maps {
  2126.  
  2127. map0 {
  2128. trip = <0x0>;
  2129. cooling-device = <0x0>;
  2130. };
  2131. };
  2132. };
  2133. };
  2134.  
  2135. display-engine {
  2136. allwinner,pipelines = <0x0>;
  2137. };
  2138.  
  2139. ahci-5v {
  2140. pinctrl-0 = <0x0>;
  2141. gpio = <0x0>;
  2142. };
  2143.  
  2144. usb0-vbus {
  2145. pinctrl-0 = <0x0>;
  2146. gpio = <0x0>;
  2147. vin-supply = <0x0>;
  2148. };
  2149.  
  2150. usb1-vbus {
  2151. pinctrl-0 = <0x0>;
  2152. gpio = <0x0>;
  2153. };
  2154.  
  2155. usb2-vbus {
  2156. pinctrl-0 = <0x0>;
  2157. gpio = <0x0>;
  2158. };
  2159.  
  2160. leds {
  2161.  
  2162. status {
  2163. gpios = <0x0>;
  2164. };
  2165. };
  2166.  
  2167. mmc0_pwrseq {
  2168. pinctrl-0 = <0x0>;
  2169. reset-gpios = <0x0>;
  2170. };
  2171.  
  2172. onewire {
  2173. gpios = <0x0>;
  2174. pinctrl-0 = <0x0>;
  2175. };
  2176.  
  2177. wifi_reg {
  2178. vin0-supply = <0x0>;
  2179. vin1-supply = <0x0>;
  2180. };
  2181. };
  2182. };
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