solarwind

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May 5th, 2011
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  1. `timescale 1ns / 1ps
  2.  
  3. module main(   
  4.     input wire clk,
  5.     output reg [7:0] Led,
  6.     output wire [3:0] an,
  7.     output wire [6:0] seg
  8.     );
  9.    
  10.     reg [32:0] count;
  11.        
  12.     always @ (posedge clk) begin
  13.         count = count + 1;
  14.         Led[7:0] = count[27:20];       
  15.     end
  16.    
  17.     led_mux unit0(.clk(clk), .an(an), .seg(seg), .hex(16'hABCD));
  18.    
  19. endmodule
  20.  
  21. module led_mux(
  22.     input wire clk,
  23.     output reg [3:0] an,
  24.     output reg [6:0] seg,
  25.     input wire [15:0] hex
  26.     );
  27.    
  28.     reg [19:0] count;
  29.     wire [33:0] sseg_v;
  30.    
  31.     hex_to_sseg digit0(.hex(hex[3:0]), .sseg(sseg_v[7:0]));
  32.     hex_to_sseg digit1(.hex(hex[7:4]), .sseg(sseg_v[15:8]));
  33.     hex_to_sseg digit2(.hex(hex[11:8]), .sseg(sseg_v[23:16]));
  34.     hex_to_sseg digit3(.hex(hex[15:12]), .sseg(sseg_v[33:24]));
  35.    
  36.     always @ (posedge clk) begin
  37.         count = count + 1;
  38.        
  39.         case(count[15:14])
  40.             2'b00: begin an[3:0] = 4'b1110; seg [6:0] = sseg_v[6:0]; end
  41.             2'b01: begin an[3:0] = 4'b1101; seg [6:0] = sseg_v[14:8]; end
  42.             2'b10: begin an[3:0] = 4'b1011; seg [6:0] = sseg_v[22:16]; end
  43.             2'b11: begin an[3:0] = 4'b0111; seg [6:0] = sseg_v[32:24]; end
  44.             default: begin an[3:0] = 4'b1111; end
  45.         endcase
  46.     end
  47.    
  48. endmodule
  49.  
  50. module hex_to_sseg(
  51.     input wire [3:0] hex,    
  52.     output reg [7:0] sseg
  53.     );
  54.  
  55.     always @ *
  56.     begin
  57.         case(hex)
  58.             4'h0: sseg [6:0] = 7'b1000000;
  59.             4'h1: sseg [6:0] = 7'b1111001;
  60.             4'h2: sseg [6:0] = 7'b0100100;
  61.             4'h3: sseg [6:0] = 7'b0110000;
  62.             4'h4: sseg [6:0] = 7'b0011001;
  63.             4'h5: sseg [6:0] = 7'b0010010;
  64.             4'h6: sseg [6:0] = 7'b0000010;
  65.             4'h7: sseg [6:0] = 7'b1111000;
  66.             4'h8: sseg [6:0] = 7'b0000000;
  67.             4'h9: sseg [6:0] = 7'b0010000;
  68.             4'ha: sseg [6:0] = 7'b0001000;
  69.             4'hb: sseg [6:0] = 7'b0000011;
  70.             4'hc: sseg [6:0] = 7'b1000110;
  71.             4'hd: sseg [6:0] = 7'b0100001;
  72.             4'he: sseg [6:0] = 7'b0000110;             
  73.         default: sseg [6:0] = 7'b0001110; //4'hF
  74.     endcase
  75.     end
  76. endmodule
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