module stany(
input w,clk,aclr,
output reg [9:0] y);

reg [8:0] d;
(*keep*) reg[3:0] state, next;
localparam[3:0]
	s0 = 4'h0,
	s1 = 4'h1,
	s2 = 4'h2,
	s3 = 4'h3,
	s4 = 4'h4,
	s5 = 4'h5,
	s6 = 4'h6,
	s7 = 4'h7,
	s8 = 4'h8;
always @(posedge clk, negedge aclr)
if(~aclr) state<= s0;
else state <= next;

always @(*)
begin
	case(state)
	s0: if(w) next=s1;
		else next = s5;
	s1: if(w) next=s2;
		else next = s5;
	s2: if(w) next=s3;
		else next = s5;
	s3: if(w) next=s4;
		else next = s5;
	s4: if(w) next=s4;
		else next = s5;
	s5: if(~w) next=s6;
		else next = s1;
	s6: if(~w) next=s7;
		else next = s1;
	s7: if(~w) next=s8;
		else next = s1;
	s8: if(~w) next=s8;
		else next = s1;

	endcase;


end

always @(*)
	case(state)
	s0:
	begin
			y=0;
			y[0]=1'b1;
	end
	s1:
	begin
			y=0;
			y[1]=1'b1;
	end
	s2:
	begin
			y=0;
			y[2]=1'b1;
	end
	s3:
	begin
			y=0;
			y[3]=1'b1;
	end
	s4:
	begin
			y=0;
			y[4]=1'b1;
			y[9] = 1'b1;
	end
	s5:
	begin
			y=0;
			y[5]=1'b1;
	end
	s6:
	begin
			y=0;
			y[6]=1'b1;
	end
	s7:
	begin
			y=0;
			y[7]=1'b1;
	end
	s8:
	begin
			y=0;
			y[8]=1'b1;
			y[9] = 1'b1;
	end


endcase

endmodule

module zad1(
input [1:0] SW,
input [1:0] KEY,
output [9:0] LEDR);

	stany s(SW[1],KEY[0],SW[0],LEDR[9:0]);

endmodule