library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BINtoBCD is
    Port ( c  : in STD_LOGIC;
           S3 : in STD_LOGIC;
           S2 : in STD_LOGIC;
           S1 : in STD_LOGIC;
           S0 : in STD_LOGIC;
           bcd1 : out STD_LOGIC_VECTOR(3 downto 0);
           bcd0 : out STD_LOGIC_VECTOR(3 downto 0));

end BINtoBCD;

architecture Behavioral of BINtoBCD is
signal truth: std_logic_vector(4 downto 0);
signal int: unsigned(4 downto 0);
signal digit0: unsigned(4 downto 0);
signal digit1: unsigned(4 downto 0);

begin
 truth <= c & s3 & s2 & s1 & s0;
 int <= unsigned(truth);
 digit0 <= int mod 10;
 digit1 <= int / 10;

 bcd0 <= std_logic_vector(digit0(3 downto 0));
 bcd1 <= std_logic_vector(digit1(3 downto 0));

end Behavioral;