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-- Company:
-- Engineer:
--
-- Create Date:    10:28:38 01/15/2019
-- Design Name:
-- Module Name:    vgaControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vgaControler is
    Port ( CLK_50MHz : in  STD_LOGIC;
           RGB : in  STD_LOGIC_VECTOR (2 downto 0);
           VGA_R : out  STD_LOGIC;
           VGA_G : out  STD_LOGIC;
           VGA_B : out  STD_LOGIC;
           VGA_HS : out  STD_LOGIC;
           VGA_VS : out  STD_LOGIC;
           PIX_X : out  STD_LOGIC_VECTOR (9 downto 0);
           PIX_Y : out  STD_LOGIC_VECTOR (8 downto 0));
end vgaControler;

architecture Behavioral of vgaControler is
    signal clk_25 : STD_LOGIC := '0';
    signal h_cnt : integer := 0;
    signal v_cnt : integer := 0;

    signal hor_sync : STD_LOGIC := '0';
    signal ver_sync : STD_LOGIC := '0';

begin

    clk_div : process(CLK_50MHz)
    begin
        if (rising_edge(CLK_50MHZ)) then
            clk_25 <= not clk_25;
        end if;
    end process clk_div;

    counters : process(clk_25)
    begin
        if (rising_edge(clk_25)) then
            if (h_cnt < 800) then
                h_cnt <= h_cnt + 1;
            else
                h_cnt <= 0;

                if (v_cnt < 521) then
                    v_cnt <= v_cnt + 1;
                else
                    v_cnt <= 0;
                end if;
            end if;
        end if;
    end process counters;

    h_sync : process(h_cnt)
    begin
        if (h_cnt = 800) then
            hor_sync <= not hor_sync;
        end if;

        VGA_HS <= hor_sync;
    end process h_sync;

    v_sync : process(v_cnt)
    begin
        if (v_cnt = 521) then
            ver_sync <= not ver_sync;
        end if;

        VGA_VS <= ver_sync;
    end process v_sync;

    color_pixel : process(h_cnt, v_cnt, RGB)
    begin
        if ((h_cnt < 640) and (v_cnt < 480)) then
            -- color
            VGA_R <= RGB(2);
            VGA_G <= RGB(1);
            VGA_B <= RGB(0);

            -- pixel
            PIX_X <= std_logic_vector(to_unsigned(h_cnt, 10));
            PIX_Y <= std_logic_vector(to_unsigned(v_cnt, 9));
        else
            -- color
            VGA_R <= '0';
            VGA_G <= '0';
            VGA_B <= '0';

            -- pixel
            PIX_X <= std_logic_vector(to_unsigned(640, 10));
            PIX_Y <= std_logic_vector(to_unsigned(480, 9));
        end if;
    end process color_pixel;

end Behavioral;