module register_set (input [4:0] a1, a2, a3,
                input [31:0] wd3,
                input clk, we3,
                output reg [31:0] rd1, rd2);

  reg [31:0] rf[31:0];


  always @(*)
    rf[0] = 0;

  always @(a1)
    rd1 = rf[a1];

  always @(a2)
    rd2 = rf[a2];

  always @(posedge clk)
    begin
      if ((we3 == 1) && (a3 != 0))
        rf[a3] = wd3;
      else
        rf[a3] = rf[a3];
    end

endmodule