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a guest Sep 12th, 2019 78 Never
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  1. `timescale 1ns/100ps
  2. `default_nettype none
  3.  
  4. module Circuit_1(A, B, C, F1, F2);
  5. output F1, F2;
  6. input A, B, C;
  7. wire T1, T2, T3, T4, T5, T6, T7;
  8.  
  9. // Lower group
  10. and (T4, A, B);
  11. and (T5, A, C);
  12. and (T6, B, C);
  13. or (F2, T4, T5, T6);
  14.  
  15. // Top inputs
  16. and (T2, A, B, C);
  17. or (T1, A, B, C);
  18.  
  19. // Middle section
  20. not (F2, T7);
  21. and (T3, T7);
  22.  
  23. // Top output
  24. or (F1, T2, T3);
  25.  
  26. endmodule // Circuit_1
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