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Junior_FPGA

hamming_encoder_pre

Jun 4th, 2021
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  1. library ieee;
  2. use     ieee.std_logic_1164.all;
  3. use     ieee.std_logic_arith.all;
  4. use     ieee.std_logic_misc.all;
  5. use     ieee.std_logic_unsigned.all;
  6.  
  7. -- Uncomment the following library declaration if using
  8. -- arithmetic functions with Signed or Unsigned values
  9. --use IEEE.NUMERIC_STD.ALL;
  10.  
  11. -- Uncomment the following library declaration if instantiating
  12. -- any Xilinx leaf cells in this code.
  13. --library UNISIM;
  14. --use UNISIM.VComponents.all;
  15.  
  16. entity hamming_encoder is
  17.     Port (
  18.         clk_i : in  std_logic;
  19.         rst_i : in  std_logic;
  20.  
  21.         -- inputs
  22.         dat_i : in  std_logic_vector(15 downto 0);
  23.         vld_i : in  std_logic;
  24.         rdy_o : out std_logic;
  25.  
  26.         -- outputs
  27.         dat_o : out std_logic_vector(15 downto 0);
  28.         vld_o : out std_logic;
  29.         rdy_i : in  std_logic
  30.     );
  31.  
  32. end hamming_encoder;
  33.  
  34. architecture Behavioral of hamming_encoder is
  35.  
  36. --HAMMING  
  37.  
  38. --CONSTANT
  39.     constant MAX_COUNT : integer := 1;
  40.  
  41. --RECEIVE SIG
  42.     signal data_buf   : std_logic_vector (31 downto 0);
  43.     signal count_data : integer range 0  to MAX_COUNT;
  44. --TRANSMIT SIG
  45.     signal buf_zero   : std_logic_vector (15 downto 0);
  46.  
  47. --TYPE
  48.     type   encoder_state_type is (RECEIVE_DATA, ENCRYPTION, SENDING_DATA);
  49.     signal encoder_state: encoder_state_type;
  50.  
  51. begin
  52.  
  53.     RECEIVE_PROC : process (clk_i, rst_i)
  54.     begin
  55.         if rst_i = '1' then
  56.             data_buf <= (others =>'0');
  57.             encoder_state <= RECEIVE_DATA;
  58.             rdy_o <= '0';
  59.             dat_o <= (others =>'0');
  60.             vld_o <= '0';
  61.             buf_zero <= (others =>'0');
  62.         elsif rising_edge(clk_i) then
  63.             case encoder_state is
  64.                 when RECEIVE_DATA =>
  65.                 rdy_o <= '1';
  66.                     if vld_i = '1' then
  67.                         data_buf <= data_buf(15 downto 0) & dat_i;
  68.                         if count_data = MAX_COUNT then
  69.                             count_data <= 0;
  70.                             encoder_state <= ENCRYPTION;
  71.                             rdy_o <= '0';
  72.                         else
  73.                             count_data <= count_data + 1;
  74.                         end if;
  75.                     end if;
  76.                
  77.                 when ENCRYPTION =>
  78.                     encoder_state <= SENDING_DATA;
  79.  
  80.                 when SENDING_DATA =>
  81.                     vld_o <= '1';
  82.                     if rdy_i = '1' then
  83.                         data_buf <= data_buf(15 downto 0) & buf_zero;
  84.                         dat_o <= data_buf(31 downto 16);
  85.                         if count_data = MAX_COUNT then
  86.                             count_data <= 0;
  87.                             encoder_state <= RECEIVE_DATA;
  88.                             rdy_o <= '0';
  89.                             vld_o <= '0';
  90.                         else
  91.                             count_data <= count_data + 1;
  92.                         end if;
  93.                     end if;
  94.             end case;
  95.         end if;
  96.     end process;
  97. end Behavioral;
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