`timescale 1ns / 1ps
module count_leading_zeros(x, nlz);
    input [11:0] x;
    output wire [3:0] nlz;
    assign nlz =
    (x[11])  ? 4'd0 :
    ((x[10]) ? 4'd1 :
    ((x[9])  ? 4'd2 :
    ((x[8])  ? 4'd3 :
    ((x[7])  ? 4'd4 :
    ((x[6])  ? 4'd5 :
    ((x[5])  ? 4'd6 :
    ((x[4])  ? 4'd7 : 4'd8 )))))));
endmodule