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  1. From 9596e62b8403c989bddbdfd7dbd9489781ad03ed Mon Sep 17 00:00:00 2001
  2. From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  3. Date: Fri, 2 Apr 2021 22:02:32 +0200
  4. Subject: [PATCH 5/5] net: dsa: lantiq_gswip: Configure the MAC_CTRL0 register
  5.  
  6. For each switch port (excep the CPU port) there is a MAC_CTRL0 register
  7. where various MAC related settings are configured. These include:
  8. - xMII interface mode (GMII/RGMII or MII/RMII)
  9. - Full Duplex
  10. - Flow Control
  11. - Transmit FCS
  12.  
  13. Explicitly elect "AUTO" mode for all of them when the link settings
  14. are auto-negotiated by the PHY. This brings the registers into a defined
  15. state when booting Linux, whereas before we relied on the bootloader to
  16. configure them properly.
  17.  
  18. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
  19. Cc: stable@vger.kernel.org
  20. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  21. ---
  22. drivers/net/dsa/lantiq_gswip.c | 40 +++++++++++++++++++++++++++-------
  23.  1 file changed, 32 insertions(+), 8 deletions(-)
  24.  
  25. diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
  26. index 9e29bde4f970..4f529c724e5d 100644
  27. --- a/drivers/net/dsa/lantiq_gswip.c
  28. +++ b/drivers/net/dsa/lantiq_gswip.c
  29. @@ -191,6 +191,23 @@
  30.  #define GSWIP_PCE_DEFPVID(p)       (0x486 + ((p) * 0xA))
  31.  
  32.  #define GSWIP_MAC_FLEN         0x8C5
  33. +#define GSWIP_MAC_CTRL_0p(p)       (0x903 + ((p) * 0xC))
  34. +#define  GSWIP_MAC_CTRL_0_PADEN        0x0100
  35. +#define  GSWIP_MAC_CTRL_0_FCS_EN   0x0080
  36. +#define  GSWIP_MAC_CTRL_0_FCON_MASK    0x0070
  37. +#define  GSWIP_MAC_CTRL_0_FCON_AUTO    0x0000
  38. +#define  GSWIP_MAC_CTRL_0_FCON_RX  0x0010
  39. +#define  GSWIP_MAC_CTRL_0_FCON_TX  0x0020
  40. +#define  GSWIP_MAC_CTRL_0_FCON_RXTX    0x0030
  41. +#define  GSWIP_MAC_CTRL_0_FCON_NONE    0x0040
  42. +#define  GSWIP_MAC_CTRL_0_FDUP_MASK    0x000C
  43. +#define  GSWIP_MAC_CTRL_0_FDUP_AUTO    0x0000
  44. +#define  GSWIP_MAC_CTRL_0_FDUP_EN  0x0004
  45. +#define  GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
  46. +#define  GSWIP_MAC_CTRL_0_GMII_MASK    0x0003
  47. +#define  GSWIP_MAC_CTRL_0_GMII_AUTO    0x0000
  48. +#define  GSWIP_MAC_CTRL_0_GMII_MII 0x0001
  49. +#define  GSWIP_MAC_CTRL_0_GMII_RGMII   0x0002
  50.  #define GSWIP_MAC_CTRL_2p(p)       (0x905 + ((p) * 0xC))
  51.  #define GSWIP_MAC_CTRL_2_MLEN      BIT(3) /* Maximum Untagged Frame Lnegth */
  52.  
  53. @@ -1513,14 +1530,21 @@ static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
  54.     struct gswip_priv *priv = ds->priv;
  55.  
  56.     if (!dsa_is_cpu_port(ds, port) && mode == MLO_AN_PHY) {
  57. -       u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO |
  58. -                 GSWIP_MDIO_PHY_SPEED_AUTO |
  59. -                 GSWIP_MDIO_PHY_FDUP_AUTO |
  60. -                 GSWIP_MDIO_PHY_FCONTX_AUTO |
  61. -                 GSWIP_MDIO_PHY_FCONRX_AUTO |
  62. -                 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK);
  63. -
  64. -       gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port));
  65. +       gswip_mdio_w(priv, GSWIP_MDIO_PHY_LINK_AUTO |
  66. +                GSWIP_MDIO_PHY_SPEED_AUTO |
  67. +                GSWIP_MDIO_PHY_FDUP_AUTO |
  68. +                GSWIP_MDIO_PHY_FCONTX_AUTO |
  69. +                GSWIP_MDIO_PHY_FCONRX_AUTO |
  70. +                (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK),
  71. +                GSWIP_MDIO_PHYp(port));
  72. +
  73. +       gswip_switch_w(priv, GSWIP_MAC_CTRL_0_PADEN |
  74. +                  GSWIP_MAC_CTRL_0_FCS_EN |
  75. +                  GSWIP_MAC_CTRL_0_FCON_AUTO |
  76. +                  GSWIP_MAC_CTRL_0_FDUP_AUTO |
  77. +                  GSWIP_MAC_CTRL_0_GMII_AUTO,
  78. +                  GSWIP_MAC_CTRL_0p(port));
  79. +
  80.         /* Activate MDIO auto polling */
  81.         gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0);
  82.     }
  83. --
  84. 2.31.1
  85.  
  86.  
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