library ieee;
use ieee.std_logic_1164.all;
entity Extensor is
    port
    (
        X,Y,Z,a,b           : in STD_logic_vector(3 downto 0);
        Ia,Ib,cin           : out STD_logic_vector(3 downto 0)
    );
end Extensor;

architecture Estrutural of Extensor is
begin
    ia <= (not(x) and a) or (x and y and z and not(a));
    ib <= (not(x) and not(y) and not(z) and b) or (not(x) and not(y) and z and not(b));
    cin(0) <= (y and not(z) and not(a) and b) or (x and not(y) and a and b) or (not(x) and y and not(z)) or (not(x) and not(y) and z) or (not(y) and z and b) or (not (y) and z and a) or (y and not(z) and a and not(b));
    cin(3 downto 1) <= (x and y and not(z) and not(a) and b) or (x and y and not(z) and a and not(b)) or (x and not(y) and z and b) or (x and not (y) and z and a) or (x and not (y) and a and b);
end Estrutural;