LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Lab7b IS
    PORT (
        SW : in STD_LOGIC_VECTOR(2 downto 0);
        LEDR : buffer STD_LOGIC_VECTOR(1 downto 0));
END Lab7b;

ARCHITECTURE Structure OF Lab7b IS
    SIGNAL e: STD_LOGIC;
BEGIN
    e <= SW(2);
    LEDR(0) <= NOT((SW(0) nand e) and LEDR(1));
    LEDR(1) <= NOT((SW(1) nand e) and LEDR(0));
END Structure;