DEF MUX21ALT
PORT IN I0
PORT IN I1
PORT IN S
PORT IN Q
PORT OUT Z
NET W
NET E

INST N2 NAND S I1 W
INST N3 NAND Q I0 E
INST N4 NAND W E Z

ENDDEF

DEF MUX41ALT
PORT IN A
PORT IN B
PORT IN C
PORT IN D
PORT IN S<1:0>
PORT IN E
PORT OUT Z
NET Q
NET W

INST 0 MUX21ALT A B S<0> E Q
INST 1 MUX21ALT C D S<0> E W
INST 2 MUX21 Q W S<1> Z
ENDDEF


DEF MUX81
PORT IN 0
PORT IN 1
PORT IN 2
PORT IN 3
PORT IN 4
PORT IN 5
PORT IN 6
PORT IN 7
PORT IN S2
PORT IN S1
PORT IN S0
PORT IN E
PORT OUT Z
NET Q
NET W

INST 0 MUX41ALT 0 1 2 3 S1 S0 E Q
INST 1 MUX41ALT 4 5 6 7 S1 S0 E W
INST 2 MUX21 Q W S2 Z

ENDDEF

DEF MUX81X8
PORT IN I0<7:0>
PORT IN I1<7:0>
PORT IN I2<7:0>
PORT IN I3<7:0>
PORT IN I4<7:0>
PORT IN I5<7:0>
PORT IN I6<7:0>
PORT IN I7<7:0>
PORT IN S<2:0>
PORT OUT Z<7:0>
NET E

INST 8 NOT S<0> E
INST 0 MUX81 I0<7> I1<7> I2<7> I3<7> I4<7> I5<7> I6<7> I7<7> S<2> S<1> S<0> E Z<7>
INST 1 MUX81 I0<6> I1<6> I2<6> I3<6> I4<6> I5<6> I6<6> I7<6> S<2> S<1> S<0> E Z<6>
INST 2 MUX81 I0<5> I1<5> I2<5> I3<5> I4<5> I5<5> I6<5> I7<5> S<2> S<1> S<0> E Z<5>
INST 3 MUX81 I0<4> I1<4> I2<4> I3<4> I4<4> I5<4> I6<4> I7<4> S<2> S<1> S<0> E Z<4>
INST 4 MUX81 I0<3> I1<3> I2<3> I3<3> I4<3> I5<3> I6<3> I7<3> S<2> S<1> S<0> E Z<3>
INST 5 MUX81 I0<2> I1<2> I2<2> I3<2> I4<2> I5<2> I6<2> I7<2> S<2> S<1> S<0> E Z<2>
INST 6 MUX81 I0<1> I1<1> I2<1> I3<1> I4<1> I5<1> I6<1> I7<1> S<2> S<1> S<0> E Z<1>
INST 7 MUX81 I0<0> I1<0> I2<0> I3<0> I4<0> I5<0> I6<0> I7<0> S<2> S<1> S<0> E Z<0>

ENDDEF