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  1. # This makefrag is sourced by each board's subdirectory
  2.  
  3. JOBS = 16
  4. TEMPLATE_DIR ?= $(base_dir)/boom-template
  5. ROCKET_DIR   ?= $(TEMPLATE_DIR)/rocket-chip
  6. TOP_MODULE   ?= Top
  7. CFG_PROJECT  ?= $(TOP_MODULE_PROJECT)
  8. SCALA_VERSION=2.12.4
  9. SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
  10.  
  11. base_dir = $(abspath ..)
  12. common = $(base_dir)/common
  13. common_build = $(common)/build
  14. testchipip = $(base_dir)/testchipip
  15. output_delivery = deliver_output
  16. SHELL := /bin/bash
  17.  
  18. bootrom_img = $(testchipip)/bootrom/bootrom.rv64.img $(testchipip)/bootrom/bootrom.rv32.img
  19.  
  20. ifneq ($(BOARD_MODEL),)
  21.     insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g
  22. endif
  23.  
  24. proj_name = $(BOARD)_rocketchip_$(CONFIG)
  25.  
  26. verilog_srcs = \
  27.     src/verilog/clocking.vh \
  28.     src/verilog/rocketchip_wrapper.v \
  29.     src/verilog/$(TOP_MODULE).$(CONFIG).v \
  30.     src/verilog/AsyncResetReg.v \
  31.     src/verilog/plusarg_reader.v \
  32.  
  33. bootimage = fpga-images-$(BOARD)/boot.bin
  34. ifneq ($(BOARD),zc706_MIG)
  35. bootimage: $(bootimage)
  36. else
  37. default: bitstream
  38. endif
  39.  
  40. $(addprefix src/verilog/,AsyncResetReg.v plusarg_reader.v): \
  41.     src/verilog/%.v: \
  42.     $(ROCKET_DIR)/src/main/resources/vsrc/%.v
  43.     cp $< $@
  44.  
  45. # Taken from rocket chip 2a5aeea. TODO: Maybe source this directly from makefrag?
  46. SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKET_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
  47.  
  48. ROCKET_CLASSES ?= "$(ROCKET_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKET_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
  49. FIRRTL_JAR ?= $(ROCKET_DIR)/firrtl/utils/bin/firrtl.jar
  50. FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver
  51.  
  52. $(FIRRTL_JAR): $(shell find $(ROCKET_DIR)/firrtl/src/main/scala -iname "*.scala" 2> /dev/null)
  53.     $(MAKE) -C $(ROCKET_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKET_DIR)/firrtl build-scala
  54.  
  55. .PRECIOUS: $(FIRRTL_JAR)
  56.  
  57. # Initialize rocket-chip submodule
  58. # ------------------------------------------------------------------------------
  59.  
  60. init-submodules:
  61.     cd $(base_dir) && git submodule update --init boom-template testchipip
  62.     cd $(TEMPLATE_DIR) && git submodule update --init
  63.     cd $(ROCKET_DIR) && git submodule update --init
  64.  
  65. # Specialize sources for board
  66. # ------------------------------------------------------------------------------
  67. ifneq ($(BOARD),zc706_MIG)
  68. src/verilog/rocketchip_wrapper.v: $(common)/rocketchip_wrapper.v
  69.     cp $(common)/rocketchip_wrapper.v src/verilog/
  70. endif
  71.  
  72. src/tcl/$(proj_name).tcl: $(common)/zynq_rocketchip.tcl Makefile
  73.     sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \
  74.         $(common)/zynq_rocketchip.tcl > src/tcl/$(proj_name).tcl
  75.  
  76. src/tcl/make_bitstream_$(CONFIG).tcl: $(common)/make_bitstream.tcl
  77.     sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \
  78.         $(common)/make_bitstream.tcl > src/tcl/make_bitstream_$(CONFIG).tcl
  79.  
  80. src/verilog/%.v: $(ROCKET_DIR)/vsrc/%.v
  81.     cp $< $@
  82.  
  83. $(ROCKET_DIR)/lib/firrtl.jar: $(FIRRTL_JAR)
  84.     mkdir -p $(@D)
  85.     cp $< $@
  86.  
  87. FIRRTL_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).fir
  88. ANNO_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).anno
  89. VERILOG_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).v
  90.  
  91. PACKAGES=boom-template/rocket-chip boom-template/boom testchipip
  92. SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
  93.  
  94. $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(FIRRTL_JAR)
  95.     mkdir -p $(common_build)
  96.     cd $(base_dir) && $(SBT) "runMain zynq.Generator $(common_build) \
  97.     $(TOP_MODULE_PROJECT) $(TOP_MODULE) $(CFG_PROJECT) $(CONFIG)"
  98.  
  99. .PRECIOUS: $(FIRRTL_FILE) $(ANNO_FILE)
  100.  
  101. $(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR) $(bootrom_img)
  102.     $(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE)
  103.  
  104. src/verilog/$(TOP_MODULE).$(CONFIG).v: $(VERILOG_FILE)
  105.     cp $< $@
  106.  
  107. rocket: src/verilog/$(TOP_MODULE).$(CONFIG).v
  108.  
  109. # Project generation
  110. # ------------------------------------------------------------------------------
  111. project = $(proj_name)/$(proj_name).xpr
  112. $(project): src/tcl/$(proj_name).tcl | $(verilog_srcs)
  113.     rm -rf $(proj_name)
  114.     vivado -mode tcl -source src/tcl/$(proj_name).tcl;
  115.  
  116. project: $(project)
  117.  
  118. vivado: $(project)
  119.     vivado $(project) &
  120.  
  121. bitstream = $(proj_name)/$(proj_name).runs/impl_1/rocketchip_wrapper.bit
  122. $(bitstream): src/tcl/make_bitstream_$(CONFIG).tcl $(verilog_srcs) src/constrs/base.xdc | $(project)
  123.     vivado -mode tcl -source src/tcl/make_bitstream_$(CONFIG).tcl
  124.  
  125. rocketchip_wrapper.bit: $(bitstream)
  126.     cp $< $@
  127.  
  128. bitstream: rocketchip_wrapper.bit
  129.  
  130.  
  131.  
  132. # Platform software generation
  133. # ------------------------------------------------------------------------------
  134. arm_linux_dir = $(base_dir)/common/linux-xlnx
  135. uboot_dir = $(base_dir)/common/u-boot-xlnx
  136. soft_build_dir = soft_build
  137.  
  138. arm-linux: arm-uboot # must first build uboot because we need tools
  139.     # compile kernel
  140.     git submodule update --init $(arm_linux_dir)
  141.     # no make clean included here since one copy of linux should work on all boards
  142.     cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig
  143.     cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS)
  144.     # convert zImage to uImage
  145.     cd $(arm_linux_dir) && export PATH=$(uboot_dir)/tools:$$PATH && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage
  146.     mkdir -p $(output_delivery)
  147.     cp $(arm_linux_dir)/arch/arm/boot/uImage $(output_delivery)/
  148.  
  149. arm-uboot:
  150.     # compile board-compatible u-boot
  151.     git submodule update --init $(uboot_dir)
  152.     # copy relevant configuration files
  153.     if [ -a soft_config/boards.cfg ] ; \
  154.     then \
  155.         cp soft_config/boards.cfg $(uboot_dir)/ ; \
  156.     fi;
  157.     cp soft_config/zynq_$(UBOOT_CONFIG).h $(uboot_dir)/include/configs/
  158.     # actually build
  159.     cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_$(UBOOT_CONFIG)_config
  160.     cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS)
  161.     mkdir -p $(soft_build_dir)
  162.     cp $(uboot_dir)/u-boot $(soft_build_dir)/u-boot.elf
  163.  
  164. arm-dtb:
  165.     export PATH=$(arm_linux_dir)/scripts/dtc:$$PATH && dtc -I dts -O dtb -o $(output_delivery)/devicetree.dtb soft_config/$(BOARD)_devicetree.dts
  166.  
  167.  
  168.  
  169. # Handle images and git submodule for prebuilt modules
  170. # ------------------------------------------------------------------------------
  171. ifneq ($(BOARD),zc706_MIG)
  172. images = fpga-images-$(BOARD)/boot.bif
  173. $(images):
  174.     git submodule update --init --depth=1 fpga-images-$(BOARD)
  175.  
  176. fetch-images: $(images)
  177.  
  178. $(bootimage): $(images) $(bitstream)
  179.     ln -sf ../../$(bitstream) fpga-images-$(BOARD)/boot_image/rocketchip_wrapper.bit
  180.     cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin
  181.  
  182. load-sd: $(images)
  183.     $(base_dir)/common/load_card.sh $(SD)
  184.  
  185. ramdisk-open: $(images)
  186.     mkdir ramdisk
  187.     dd if=fpga-images-$(BOARD)/uramdisk.image.gz  bs=64 skip=1 | \
  188.     gunzip -c | sudo sh -c 'cd ramdisk/ && cpio -i'
  189.  
  190. ramdisk-close:
  191.     @if [ ! -d "ramdisk" ]; then \
  192.         echo "No ramdisk to close (use make ramdisk-open first)"; \
  193.         exit 1; \
  194.     fi
  195.     sh -c 'cd ramdisk/ && sudo find . | sudo cpio -H newc -o' | gzip -9 > uramdisk.cpio.gz
  196.     mkimage -A arm -O linux -T ramdisk -d uramdisk.cpio.gz fpga-images-$(BOARD)/uramdisk.image.gz
  197.     rm uramdisk.cpio.gz
  198.     @echo "Don't forget to remove ramdisk before opening it again (sudo rm -rf ramdisk)"
  199.  
  200.  
  201. # Fetch ramdisk for user building from scratch
  202. # ------------------------------------------------------------------------------
  203. s3_url = https://s3-us-west-1.amazonaws.com/riscv.org/fpga-zynq-files
  204. ramdisk_url = $(s3_url)/uramdisk.image.gz
  205. fetch-ramdisk:
  206.     mkdir -p $(output_delivery)
  207.     curl $(ramdisk_url) > $(output_delivery)/uramdisk.image.gz
  208.  
  209.  
  210. # Rebuild from bif for user building from scratch
  211. # ------------------------------------------------------------------------------
  212. $(output_delivery)/boot.bin:
  213.     cd $(output_delivery); bootgen -image output.bif -w -o boot.bin
  214. endif
  215.  
  216. # Build riscv-fesvr for zynq
  217. # ------------------------------------------------------------------------------
  218.  
  219. fesvr-main = fesvr-zynq
  220. fesvr-srcs = \
  221.     $(common)/csrc/fesvr_zynq.cc \
  222.     $(common)/csrc/zynq_driver.cc \
  223.     $(testchipip)/csrc/blkdev.cc \
  224.  
  225. fesvr-hdrs = \
  226.     $(common)/csrc/zynq_driver.h \
  227.     $(testchipip)/csrc/blkdev.h \
  228.  
  229. fesvr-lib = $(common_build)/libfesvr.so
  230.  
  231. CXX_FPGA      = arm-xilinx-linux-gnueabi-g++
  232. CXXFLAGS_FPGA = -O2 -std=c++11 -Wall -L$(common_build) -lfesvr \
  233.                 -Wl,-rpath,/usr/local/lib \
  234.         -I $(common)/csrc -I $(testchipip)/csrc \
  235.         -I $(ROCKET_DIR)/riscv-tools/riscv-fesvr/ \
  236.         -Wl,-rpath,/usr/local/lib \
  237.  
  238. $(fesvr-lib):
  239.     mkdir -p $(common_build)
  240.     cd $(common_build) && \
  241.     $(ROCKET_DIR)/riscv-tools/riscv-fesvr/configure \
  242.         --host=arm-xilinx-linux-gnueabi && \
  243.     make libfesvr.so
  244.  
  245. $(common_build)/$(fesvr-main): $(fesvr-lib) $(fesvr-srcs) $(fesvr-hdrs)
  246.     $(CXX_FPGA) $(CXXFLAGS_FPGA) -o $(common_build)/$(fesvr-main) $(fesvr-srcs)
  247.  
  248. fesvr-zynq: $(common_build)/$(fesvr-main)
  249.  
  250. # Fetch pre-built risc-v linux binary and root fs from S3
  251. # ------------------------------------------------------------------------------
  252.  
  253. riscv_root_bin = $(s3_url)/root.bin
  254. ifeq ($(BOARD), zybo)
  255.     riscv_vmlinux = $(s3_url)/vmlinux_nofpu
  256. else
  257.     riscv_vmlinux = $(s3_url)/vmlinux
  258. endif
  259. sd_riscv = fpga-images-$(BOARD)/riscv
  260. sd_riscv_scratch = $(output_delivery)/riscv
  261.  
  262. fetch-riscv-linux:
  263.     mkdir -p $(sd_riscv)
  264.     curl $(riscv_root_bin) > $(sd_riscv)/root.bin
  265.     curl $(riscv_vmlinux) > $(sd_riscv)/vmlinux
  266.  
  267. fetch-riscv-linux-deliver:
  268.     mkdir -p $(sd_riscv_scratch)
  269.     curl $(riscv_root_bin) > $(sd_riscv_scratch)/root.bin
  270.     curl $(riscv_vmlinux) > $(sd_riscv_scratch)/vmlinux
  271.  
  272. clean:
  273.     rm -f *.log *.jou *.str
  274.     rm -rf csrc simv-* output ucli.key vc_hdrs.h DVEfiles
  275.  
  276. .PHONY: vivado project init-submodules rocket fesvr-zynq fetch-images load-sd ramdisk-open ramdisk-close clean
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