LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY test_bench IS
END ENTITY test_bench;
ARCHITECTURE a OF test_bench IS

-------------------------------------------------------------------
    signal tbclk : std_logic;
    signal tbdin : std_logic:='0';
    signal tbdintabl : integer := 0;
    signal tbrst : std_logic:='0';
    signal tbrfd : std_logic:='1';
    signal tbdv :  std_logic:='1';
    signal tbdout : std_logic_vector(999 downto 0);

    component readfile is
        generic(
            file_name : string := "C:\Users\Alex\peremezh.dat");
        port(
            data : out integer := 0;
            dv: out std_logic;
            rst : in std_logic;
            rfd : in std_logic;
            clk : in std_logic);
        end component;

    component koder IS
    port(
           clk : in STD_LOGIC;
           dintabl : in integer := 0;
           din: in std_logic := '0');
    end component;

    component peremezh is
     Port (clk : in std_logic;
           din : in std_logic;
           dintabl : in integer := 0;
           dout : out std_logic_vector(999 downto 0));
    end component;

-----------------------------------------------------------------

BEGIN

generate_clk : process begin
    loop
        tbclk <= '1';
    wait for 25 ns;
        tbclk <= '0';
    wait for 25 ns;
    end loop;
end process;

process(tbclk) begin
    if rising_edge(tbclk) then
        if tbdin = '1' then
            tbdin <= '0';
        else
            tbdin <= '1';
        end if;
    end if;
end process;

read : ReadFile
    port map (
        clk => tbclk,
        rfd => tbrfd,
        rst => tbrst,
        data => tbdintabl);

tabl : peremezh
    port map(
        clk => tbclk,
        din => tbdin,
        dintabl => tbdintabl,
        dout => tbdout);

uut : koder
    Port map (
         clk => tbclk,
         dintabl => tbdintabl,
         din => tbdin);
END  a;