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exe4

PauloTiming Oct 21st, 2019 88 Never
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  1. library IEEE;
  2. use IEEE.Std_Logic_1164.all;
  3. use IEEE.std_logic_unsigned.all; -- necessário para o +
  4.  
  5. entity topo is
  6. port (SW: in std_logic_vector(9 downto 0);
  7.     HEX0: out std_logic_vector(6 downto 0);
  8.     HEX1: out std_logic_vector(6 downto 0);
  9.     KEY: in std_logic_vector(3 downto 0);
  10.     LEDR: out std_logic_vector(7 downto 0);
  11.     clock_50: in std_logic
  12.     );
  13. end topo;
  14.  
  15. architecture logic of topo is
  16.     signal A:std_logic_vector(7 downto 0);
  17.     signal sel:std_logic_vector(1 downto 0);
  18.     signal F00,F01,F10,F11,F,G,S:std_Logic_vector(7 downto 0);
  19.     signal G0,G1:std_logic_vector(3 downto 0);
  20.     signal BTN0, BTN1, BTN2, BTN3:std_logic;
  21.    
  22.     component mux
  23.     port (F00,F01,F10,F11: in std_logic_vector(7 downto 0);
  24.     sel: in std_Logic_vector(1 downto 0);
  25.     F: out std_logic_vector(7 downto 0));
  26.     end component;
  27.    
  28.     component ButtonSync
  29.     port
  30.     (
  31.         KEY0, KEY1, KEY2, KEY3, CLK: in std_logic;
  32.         BTN0, BTN1, BTN2, BTN3: out std_logic
  33.     );
  34.     end component;
  35.    
  36.     component sum
  37.     port (A: in std_logic_vector(7 downto 0);
  38.         B: in std_logic_vector(7 downto 0);
  39.         G: out std_logic_vector(7 downto 0));
  40.     end component;
  41.  
  42.    
  43.     component decod7seg
  44.     port (G: in std_logic_vector(3 downto 0);
  45.         HEX: out std_logic_vector(6 downto 0));
  46.     end component;
  47.    
  48.     component registrador
  49.     port (CLK, RST, EN: in std_logic;
  50.           D: in std_logic_vector(7 downto 0);
  51.           Q: out std_logic_vector(7 downto 0));
  52.     end component;  
  53.  
  54.    
  55. begin
  56.     A<= SW(7 downto 0);
  57.     sel<= SW(9 downto 8);
  58.     F10<= '0' & G(7 downto 1);
  59.     F11<= G(6 downto 0) & '0';
  60.     F00<= A + G;
  61.     F01<= A;
  62.     MUX1:mux port map (F00,F01,F10,F11,sel,F);
  63.     SUM1:sum port map (g,F01,S);
  64.     G1 <= G(7 downto 4);
  65.     G0 <= G(3 downto 0);
  66.     DEC1:decod7seg port map(G1,HEX1);
  67.     DEC0:decod7seg port map(G0,HEX0);
  68.     REGIST: registrador port map (clock_50, BTN0, BTN1, S, G);
  69.     BTSYNC: ButtonSync port map (KEY(0), KEY(1), KEY(2), KEY(3), clock_50, BTN0, BTN1, BTN2, BTN3);
  70.     LEDR(7 downto 0)<=G;
  71. -- 
  72. end logic;
  73.  
  74. -----------------------------------------
  75.  
  76. library IEEE;
  77. use IEEE.Std_Logic_1164.all;
  78. use IEEE.std_logic_unsigned.all; -- necessário para o +
  79.  
  80. entity mux is
  81. port (F00,F01,F10,F11: in std_logic_vector(7 downto 0);
  82.     sel: in std_Logic_vector(1 downto 0);
  83.     F: out std_logic_vector(7 downto 0)
  84.     );
  85. end mux;
  86.  
  87. architecture multiplexador of mux is
  88. begin
  89.     F<= F00 when sel="00" else
  90.             F01 when sel="01" else
  91.             F10 when sel="10" else
  92.             F11;
  93. end multiplexador;
  94.  
  95.  
  96.  
  97.  
  98.  
  99.  
  100.  
  101. library IEEE;
  102. use IEEE.Std_Logic_1164.all;
  103. use IEEE.std_logic_unsigned.all; -- necessário para o +
  104.  
  105. entity sum is
  106. port (A: in std_logic_vector(7 downto 0);
  107.     B: in std_logic_vector(7 downto 0);
  108.     G: out std_logic_vector(7 downto 0)
  109.     );
  110. end sum;
  111.  
  112. architecture circuito of sum is
  113. begin
  114.     G <= A + B;
  115. end circuito;
  116.  
  117.  
  118.  
  119.  
  120.  
  121.  
  122.  
  123.  
  124.  
  125.  
  126. library ieee;
  127. use ieee.std_logic_1164.all;
  128.  
  129. entity registrador is
  130.     port (CLK, RST, EN:  in std_logic;
  131.           D:  in std_logic_vector(7 downto 0);
  132.           Q: out std_logic_vector(7 downto 0)            
  133.           );
  134. end registrador;
  135.  
  136. architecture behv of registrador is
  137. begin      
  138.     process(CLK, D, RST, EN)          
  139.     begin                  
  140.         if RST = '0' then
  141.             Q <= "00000000";
  142.             elsif (CLK'event and CLK = '1') then
  143.                 if EN = '1' then
  144.                 Q <= D;
  145.                 end if;              
  146.         end if;            
  147.     end process;
  148. end behv;
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