exe4

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all; -- necessário para o +

entity topo is
port (SW: in std_logic_vector(9 downto 0);
	HEX0: out std_logic_vector(6 downto 0);
	HEX1: out std_logic_vector(6 downto 0);
	KEY: in std_logic_vector(3 downto 0);
	LEDR: out std_logic_vector(7 downto 0);
	clock_50: in std_logic
	);
end topo;

architecture logic of topo is
	signal A:std_logic_vector(7 downto 0);
	signal sel:std_logic_vector(1 downto 0);
	signal F00,F01,F10,F11,F,G,S:std_Logic_vector(7 downto 0);
	signal G0,G1:std_logic_vector(3 downto 0);
	signal BTN0, BTN1, BTN2, BTN3:std_logic;

	component mux
	port (F00,F01,F10,F11: in std_logic_vector(7 downto 0);
	sel: in std_Logic_vector(1 downto 0);
	F: out std_logic_vector(7 downto 0));
	end component;

	component ButtonSync
	port
	(
		KEY0, KEY1, KEY2, KEY3, CLK: in std_logic;
		BTN0, BTN1, BTN2, BTN3: out std_logic
	);
	end component;

	component sum
	port (A: in std_logic_vector(7 downto 0);
		B: in std_logic_vector(7 downto 0);
		G: out std_logic_vector(7 downto 0));
	end component;


	component decod7seg
	port (G: in std_logic_vector(3 downto 0);
		HEX: out std_logic_vector(6 downto 0));
	end component;

	component registrador
    port (CLK, RST, EN: in std_logic;
          D: in std_logic_vector(7 downto 0);
          Q: out std_logic_vector(7 downto 0));
    end component;


begin
	A<= SW(7 downto 0);
	sel<= SW(9 downto 8);
	F10<= '0' & G(7 downto 1);
	F11<= G(6 downto 0) & '0';
	F00<= A + G;
	F01<= A;
	MUX1:mux port map (F00,F01,F10,F11,sel,F);
	SUM1:sum port map (g,F01,S);
	G1 <= G(7 downto 4);
	G0 <= G(3 downto 0);
	DEC1:decod7seg port map(G1,HEX1);
	DEC0:decod7seg port map(G0,HEX0);
	REGIST: registrador port map (clock_50, BTN0, BTN1, S, G);
	BTSYNC: ButtonSync port map (KEY(0), KEY(1), KEY(2), KEY(3), clock_50, BTN0, BTN1, BTN2, BTN3);
	LEDR(7 downto 0)<=G;
--
end logic;

-----------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all; -- necessário para o +

entity mux is
port (F00,F01,F10,F11: in std_logic_vector(7 downto 0);
	sel: in std_Logic_vector(1 downto 0);
	F: out std_logic_vector(7 downto 0)
	);
end mux;

architecture multiplexador of mux is
begin
	F<= F00 when sel="00" else
			F01 when sel="01" else
			F10 when sel="10" else
			F11;
end multiplexador;







library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all; -- necessário para o +

entity sum is
port (A: in std_logic_vector(7 downto 0);
	B: in std_logic_vector(7 downto 0);
	G: out std_logic_vector(7 downto 0)
	);
end sum;

architecture circuito of sum is
begin
	G <= A + B;
end circuito;










library ieee;
use ieee.std_logic_1164.all;

entity registrador is
    port (CLK, RST, EN:  in std_logic;
          D:  in std_logic_vector(7 downto 0);
          Q: out std_logic_vector(7 downto 0)
          );
end registrador;

architecture behv of registrador is
begin
    process(CLK, D, RST, EN)
    begin
        if RST = '0' then
            Q <= "00000000";
            elsif (CLK'event and CLK = '1') then
                if EN = '1' then
                Q <= D;
                end if;
        end if;
    end process;
end behv;