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- #ifndef __SPI_FLASH_CONFIG_H
- #define __SPI_FLASH_CONFIG_H
- #include "stm32f4xx.h"
- #define USE_DMA
- /* M25P SPI Flash supported commands */
- #define sFLASH_CMD_WRITE 0x02 /* Write to Memory instruction */
- #define sFLASH_CMD_WRSR 0x01 /* Write Status Register instruction */
- #define sFLASH_CMD_WREN 0x06 /* Write enable instruction */
- #define sFLASH_CMD_READ 0x03 /* Read from Memory instruction */
- #define sFLASH_CMD_RDSR 0x05 /* Read Status Register instruction */
- #define sFLASH_CMD_RDID 0x9F /* Read identification */
- #define sFLASH_CMD_SE 0xD8 /* Sector Erase instruction */
- #define sFLASH_CMD_SSE 0x20 /* Small Sector Erase instruction (4K-byte) */
- #define sFLASH_CMD_BE 0xC7 /* Bulk Erase instruction */
- #define sFLASH_WIP_FLAG 0x01 /* Write In Progress (WIP) flag */
- #define sFLASH_DUMMY_BYTE 0xFF /* Just a high level */
- #define sFLASH_SPI_PAGESIZE 0x100
- #define sFLASH_SPI_MASK (sFLASH_SPI_PAGESIZE - 1U)
- #define sFLASH_M25P128_ID 0x202018
- #define sFLASH_M25P64_ID 0x202017
- #define sFLASH_GD25Q127C_ID 0xC84018
- /* DMA defs */
- #define sFLASH_DMA DMA2
- #define sFLASH_DMA_CLK RCC_AHB1Periph_DMA2
- #define sFLASH_DMA_CLK_ENR RCC->AHB1ENR
- #define sFLASH_DMA_TX_FLAG_HT DMA_FLAG_HTIF3
- #define sFLASH_DMA_TX_FLAG_TC DMA_FLAG_TCIF3
- #define sFLASH_DMA_TX_FLAG_GL (DMA_FLAG_HTIF3 | DMA_FLAG_TCIF3)
- #define sFLASH_DMA_RX_FLAG_HT DMA_FLAG_HTIF0
- #define sFLASH_DMA_RX_FLAG_TC DMA_FLAG_TCIF0
- #define sFLASH_DMA_RX_FLAG_GL (DMA_FLAG_HTIF0 | DMA_FLAG_TCIF0)
- #define sFLASH_DMA_TX_CHANNEL DMA_Channel_3
- #define sFLASH_DMA_RX_CHANNEL DMA_Channel_3
- #define sFLASH_DMA_TX_STREAM DMA2_Stream3
- #define sFLASH_DMA_RX_STREAM DMA2_Stream0
- #define sFLASH_DMA_ISR LISR
- #define sFLASH_DMA_IFCR LIFCR
- #define DMA_CCR_EN DMA_SxCR_EN
- #define DMA_CCR_DIR DMA_SxCR_DIR
- #define DMA_CCR_MINC DMA_SxCR_MINC
- #define CCR CR
- #define CNDTR NDTR
- #define CPAR PAR
- #define CMAR M0AR
- /* M25P FLASH SPI Interface pins */
- #define sFLASH_SPI SPI1
- #define sFLASH_SPI_CLK RCC_APB2Periph_SPI1
- #define sFLASH_SPI_CLK_ENR RCC->APB2ENR
- #define sFLASH_SPI_IRQn SPI1_IRQn
- #define sFLASH_SPI_IRQHandler SPI1_IRQHandler
- #define sFLASH_SPI_SCK_PIN GPIO_Pin_5
- #define sFLASH_SPI_SCK_GPIO_PORT GPIOA
- #define sFLASH_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA
- #define sFLASH_SPI_SCK_SOURCE GPIO_PinSource5
- #define sFLASH_SPI_SCK_AF GPIO_AF_SPI1
- #define sFLASH_SPI_MISO_PIN GPIO_Pin_6
- #define sFLASH_SPI_MISO_GPIO_PORT GPIOA
- #define sFLASH_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA
- #define sFLASH_SPI_MISO_SOURCE GPIO_PinSource6
- #define sFLASH_SPI_MISO_AF GPIO_AF_SPI1
- #define sFLASH_SPI_MOSI_PIN GPIO_Pin_7
- #define sFLASH_SPI_MOSI_GPIO_PORT GPIOA
- #define sFLASH_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA
- #define sFLASH_SPI_MOSI_SOURCE GPIO_PinSource7
- #define sFLASH_SPI_MOSI_AF GPIO_AF_SPI1
- #define sFLASH_CS_PIN GPIO_Pin_4
- #define sFLASH_CS_GPIO_PORT GPIOA
- #define sFLASH_CS_GPIO_CLK RCC_AHB1Periph_GPIOA
- #define sFLASH_GPIO_CLK_ENR RCC->AHB1ENR
- #define SAME_PINS_PORT //If all SPI pins are on the same port.
- /* Select sFLASH: Chip Select pin low */
- #define sFLASH_CS_LOW() sFLASH_CS_GPIO_PORT->BSRRH = sFLASH_CS_PIN;
- /* Deselect sFLASH: Chip Select pin high */
- #define sFLASH_CS_HIGH() sFLASH_CS_GPIO_PORT->BSRRL = sFLASH_CS_PIN;
- #define sFLASH_SEND_BYTE(x, y) SPI_I2S_SendData(x, y)
- #define sFLASH_RECEIVE_BYTE(x) SPI_I2S_ReceiveData(x)
- #endif /* __SPI_FLASH_CONFIG_H */
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