library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

ENTITY full_adder IS

    PORT(a:    IN STD_LOGIC;
         b:    IN STD_LOGIC;
         cin:  IN STD_LOGIC;
         cout: OUT STD_LOGIC;
         y:    OUT STD_LOGIC);

END full_adder;

ARCHITECTURE arch_full_adder of full_adder is
BEGIN
  y <= (a xor b) xor cin;
  cout <= ((a xor b) and cin) or (a and b);
END arch_full_adder;





library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

ENTITY serial_adder_subtracter_saturate IS
  GENERIC (WIDTH:INTEGER);
  PORT(a:   IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
       b:   IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
       saturate: IN STD_LOGIC;
       add_sub: IN STD_LOGIC;
       clk:     IN STD_LOGIC;
       reset: IN STD_LOGIC;
       start: IN STD_LOGIC;
       y:   OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
       overflow:OUT STD_LOGIC;
       finished:OUT STD_LOGIC);
END serial_adder_subtracter_saturate;

ARCHITECTURE arch_serial_adder_subtracter_saturate OF serial_adder_subtracter_saturate IS
  COMPONENT full_adder IS
    PORT(a:    IN STD_LOGIC;
         b:    IN STD_LOGIC;
         cin:  IN STD_LOGIC;
         cout: OUT STD_LOGIC;
         y:    OUT STD_LOGIC);
  END COMPONENT full_adder;

  SIGNAL filling:STD_LOGIC_VECTOR(WIDTH-2 DOWNTO 0);
  SIGNAL overflowed:STD_LOGIC;
  SIGNAL MSB:STD_LOGIC;
  SIGNAL sat_over:STD_LOGIC;
  SIGNAL y_tmp:STD_LOGIC;
  SIGNAL tmp_fill:STD_LOGIC_VECTOR(WIDTH-2 DOWNTO 0);
  SIGNAL ai:STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
  SIGNAL bi:STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
  SIGNAL yi:STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
  SIGNAL cini:STD_LOGIC;
  SIGNAL couti:STD_LOGIC;


  BEGIN

    full_adder0:COMPONENT full_adder
      PORT MAP (a=>ai(0),
                b=>bi(0),
                cin=>cini,
                cout=>couti,
                y=>y_tmp);

    --subtrahera

    tmp_fill <= (OTHERS=>'0');


    clk_proc:PROCESS(clk) IS
     VARIABLE counter:NATURAL:=WIDTH;
       BEGIN
       IF rising_edge(clk) then
         IF reset='1' then
           yi <= (OTHERS=>'0');
           ai <= (OTHERS=>'0');
           bi <= (OTHERS=>'0');
           y <= (OTHERS=>'0');
           counter:=0;
           cini<='0';
           finished <='0';


         ELSIF start='1' THEN
           ai <= a;
           IF add_sub='1' then
            bi <= b;
           else
             bi<=STD_LOGIC_VECTOR(SIGNED(NOT(b)) + SIGNED(tmp_fill & '1'));
           end if;
           yi <= (OTHERS=>'0');
           cini <= '0';
           counter :=0;
           finished <='0';

         ELSIF (counter < WIDTH) THEN
             ai <= '0' & ai(WIDTH-1 DOWNTO 1);
             bi <= '0' & bi(WIDTH-1 DOWNTO 1);
             overflowed <= couti XOR cini;
             cini <= couti;
             counter:=counter + 1;
             yi <= y_tmp & yi(WIDTH-1 DOWNTO 1);
         ELSE
            --overflow
           IF (saturate and overflowed and yi(WIDTH-1)) = '1' then -- TO BIG NUMBER, SETS y = 01111111 = 127
             y <= (OTHERS=>'1');
             y(WIDTH-1)<='0';
           ELSIF (saturate and overflowed and NOT(yi(WIDTH-1))) = '1' then -- TO SMALL NUMBER, SETS y = 10000000 = -128
             y <= (OTHERS=>'0');
             y(WIDTH-1)<='1';

           ELSE
            y<=yi;
           END IF;

           overflow<=overflowed;
           counter:=0;
           finished<='1';
         END IF;
     END IF;
       END PROCESS clk_proc;

END arch_serial_adder_subtracter_saturate;