verilog

module clock_divider
{
    //fill out the i/o
    //inputs
    input hw_clk, // hardware clock
    input [9:0] tp, // toggle period // max 1000
    input rst, // reset signal
    //outputs
    output reg clk_out; // clock output
};

parameter FHP = 0;
parameter SHP = 1;

//declare a counter signal to count elapsed hardware clock periods (assume that the counter signal is initialized to 0)

reg state = FHP;
reg [10:0] counter = 0; // max 2000

always @ (posedge hw_clk or posedge rst)
begin
    //write code to increment the counter
    if(rst == 1'b1)
    begin
        counter <= 1;
    end

    else if(rst == 1'b0)
    begin
        counter <= counter + 1;
    end
end

always @ (posedge hw_clk or posedge rst)
begin
    //write the state machine
    if(rst == 1'b1)
    begin
        state <= FHP;
    end

    else if(rst == 1'b0)
    begin
        case (state)
        begin
            FHP:
            begin
                if(counter == tp)
                begin
                    state <= SHP
                end
                clk_out <= 1b'0;
            end

            SHP:
            begin
                if(counter == (tp << 2)) // twice tp
                begin
                    counter <= 0;
                    state <= FHP;
                end
                clk_out <= 1b'1;
            end
        end
    end
end

endmodule