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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 00:05:07 04/12/2019
- -- Design Name:
- -- Module Name: DATAPATH - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- ---- Uncomment the following library declaration if instantiating
- ---- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity DATAPATH is
- Port ( Clk : in STD_LOGIC;
- address : out STD_LOGIC_VECTOR (31 downto 0);
- instr : out STD_LOGIC_VECTOR (31 downto 0);
- result : out STD_LOGIC_VECTOR (31 downto 0));
- end DATAPATH;
- architecture Behavioral of DATAPATH is
- signal program_counter: STD_LOGIC_VECTOR(31 downto 0 );
- signal nxt_pr_counter: STD_LOGIC_VECTOR(31 downto 0 );
- signal const_f : STD_LOGIC_VECTOR(31 downto 0);
- signal op : STD_LOGIC_VECTOR(5 downto 0);
- signal rs : STD_LOGIC_VECTOR (4 downto 0);
- signal rd : STD_LOGIC_VECTOR (4 downto 0);
- signal instrukcija : STD_LOGIC_VECTOR (31 downto 0);
- signal regiDst : std_logic;
- signal brranch : std_logic;
- signal memoRead : std_logic;
- signal memoToReg : std_logic;
- signal ALUope : std_logic_vector(1 DOWNTO 0);
- signal memoWrite : std_logic;
- signal ALUsorc : std_logic;
- signal regiWrite : std_logic;
- signal destReg : STD_LOGIC_VECTOR (4 downto 0);
- signal readRegi : STD_LOGIC_VECTOR (4 downto 0);
- signal operation : STD_LOGIC;
- signal procit2 : STD_LOGIC_VECTOR(31 downto 0);
- signal prosirenaVr : STD_LOGIC_VECTOR(31 downto 0);
- signal readDat1 : STD_LOGIC_VECTOR (31 downto 0);
- signal readDat2 : STD_LOGIC_VECTOR (31 downto 0);
- signal extended : STD_LOGIC_VECTOR(31 downto 0);
- begin
- Brojac: entity work.PC(Behavioral)
- PORT MAP(
- clk => Clk,
- pc_in => nxt_pr_counter,
- pc_out => program_counter
- );
- MemorijaInstrukcija: entity work.MEMORYINSTRUCTION(Behavioral)
- PORT MAP(
- PC => program_counter,
- instruction => instrukcija
- );
- instr <= instrukcija;
- op <= instrukcija(31 downto 26);
- Kontrola: entity work.CONTROL(Behavioral)
- PORT MAP(
- opcode => op,
- regDst => regiDst,
- branch => brranch,
- memRead => memoRead,
- memToReg => memoToReg,
- ALUop => ALUope,
- memWrite => memoWrite,
- ALUsrc => ALUsorc,
- regWrite => regiWrite
- );
- Mux: entity work.MUX2_1(Behavioral)
- PORT MAP(
- mux_in1 => instrukcija(20 downto 16),
- mux_in2 => instrukcija(15 downto 11),
- mux_ct1 => regiDst,
- mux_out => destReg
- );
- process(Clk)
- begin
- IF regiDst = '1' then
- readRegi <= instrukcija(20 downto 16);
- else
- readRegi <= instrukcija(15 downto 11);
- end if;
- end process;
- Registri: entity work.REGFILE(Behavioral)
- PORT MAP(
- readRegister1 => instrukcija(25 downto 21),
- readRegister2 => readRegi,
- writeRegister => destReg,
- writeData => x"12345678",
- registerWrite => regiWrite,
- clock => Clk,
- readData1 => readDat1,
- readData2 => procit2
- );
- Prosirenje: entity work.SIGNEXTEND(Behavioral)
- PORT MAP(
- se_in => instrukcija(15 downto 0),
- se_out => prosirenaVr
- );
- AluKontrola: entity work.ALUControl(Behavioral)
- PORT MAP(
- ALUOp => ALUope,
- funct => instrukcija(5 downto 0),
- oper => operation
- );
- Mux2: entity work.MUX2_1_imm(Behavioral)
- PORT MAP(
- mux_in1 => procit2,
- mux_in2 => prosirenaVr,
- mux_ct1 => ALUsorc,
- mux_out => readDat2
- );
- ALU: entity work.ALU(Behavioral)
- PORT MAP(
- a1 => readDat1,
- a2 => readDat2,
- alu_control => operation,
- alu_result => result
- );
- BrojacAdder: entity work.PCADDER(Behavioral)
- PORT MAP(
- cur_address => program_counter,
- const_four => const_f,
- next_address => nxt_pr_counter
- );
- address <= nxt_pr_counter;
- end Behavioral;
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