diff --git a/system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h b/system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h
index 6ab2fb48..de0f1102 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h
@@ -362,6 +362,13 @@ typedef struct
   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+       uint32_t RESERVED4;  /*!< Reserved,                                                  Address offset: 0x48 */
+       uint32_t RESERVED5;  /*!< Reserved,                                                  Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
 } RTC_TypeDef;

 /**
@@ -3361,6 +3368,7 @@ typedef struct
 */
 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
+#define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */

 /********************  Bits definition for RTC_TR register  ******************/
 #define RTC_TR_PM_Pos                (22U)
@@ -3810,6 +3818,34 @@ typedef struct
 #define RTC_ALRMASSR_SS_Msk          (0x7FFFU << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk

+/********************  Bits definition for RTC_BKP0R register  ***************/
+#define RTC_BKP0R_Pos                (0U)
+#define RTC_BKP0R_Msk                (0xFFFFFFFFU << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                    RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ***************/
+#define RTC_BKP1R_Pos                (0U)
+#define RTC_BKP1R_Msk                (0xFFFFFFFFU << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                    RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ***************/
+#define RTC_BKP2R_Pos                (0U)
+#define RTC_BKP2R_Msk                (0xFFFFFFFFU << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                    RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ***************/
+#define RTC_BKP3R_Pos                (0U)
+#define RTC_BKP3R_Msk                (0xFFFFFFFFU << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                    RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ***************/
+#define RTC_BKP4R_Pos                (0U)
+#define RTC_BKP4R_Msk                (0xFFFFFFFFU << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                    RTC_BKP4R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       0x00000005U
+
 /*****************************************************************************/
 /*                                                                           */
 /*                        Serial Peripheral Interface (SPI)                  */