SevenSegmentDecoder

--SEVEN-SEGMENT DECODER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY SevenSegmentDecoder IS
 PORT (SW : IN STD_LOGIC_VECTOR(0 TO 2); --INPUTS
        HEX0: OUT STD_LOGIC_VECTOR(0 TO 6)); --SEGMENTS, HEX0 IS ON WHEN IT'S PUT TO 0
END SevenSegmentDecoder;
ARCHITECTURE structure OF SevenSegmentDecoder IS
BEGIN --forcing to 1 the segments we need to turn off
 HEX0(0)<=((SW(2) NOR SW(1))NOR SW(0)) OR ((SW(2) NOR SW(0)) AND SW(1))  OR SW(2);
 HEX0(1)<=((SW(2) NOR SW(1)) AND SW(0)) OR ((SW(2) NOR SW(0)) AND SW(1)) OR SW(2);
 HEX0(2)<=((SW(2) NOR SW(1)) AND SW(0)) OR ((SW(2) NOR SW(0)) AND SW(1)) OR SW(2);
 HEX0(3)<=((SW(2) NOR SW(1))NOR SW(0)) OR SW(2);
 HEX0(4)<= SW(2);
 HEX0(5)<= SW(2);
 HEX0(6)<=((SW(2) NOR SW(0)) AND SW(1)) OR ((SW(1) AND SW(0)) NAND(SW(2))) OR SW(2);
END structure;
--blank when 100,101,110,111, so when C2 is 1, that's why we need to add OR SW(2) everywhere