Calc Numerice Lab06

module fact;

task factorial;
    input [3:0] n;
    output [31:0] outfact;
    integer count;
    begin
      outfact = 1;
      for(count =n; count > 0; count= count-1)
      outfact = outfact * count;
      end
endtask

initial
  begin: init1
    reg [3:0] n;
    reg [31:0] result;
    n = 4'b0101;
    factorial(n, result);
    $display("n=%d fact=%d", n, result);
  end
endmodule


((B or C) and (notA)) or (not(A or B))

module XOR(a, b, w1);

  input a, b;
  output reg w1;

  always @(a or b)
  begin
    w1 = a ^ b;
  end

endmodule

module AND(c, d, w2);

  input c, d;
  output reg w2;

  always @(c or d)
  begin
    w2 = c & d;
  end
endmodule

module OR(e, f, w3);

  input e, f;
  output reg w3;

  always @(e or f)
  begin
    w3 = e | f;
  end
endmodule

module NOR(h, i, w4);
    input h, i;
    output reg w4;

    always @(h or i)
    begin
      w4 = ~(h | i);
    end
endmodule

module something(a, b, c, out);

  input a, b, c;
  output out;
  wire w1, w2, w3;
  OR or1(b, c, w1);
  AND and1(w1, ~a, w2);
  NOR nor1(a, b, w3);
  OR or2(w2, w3, out);


endmodule

module Testbench;
  reg a, b, c;
  wire cout;

 something p(a, b, c, cout);
 initial
  begin
   a = 0;
    b = 0;
    c = 0;
    #1 $display("S=%b", cout);

   a = 1;
    b = 1;
    c = 1;
    #1 $display("S=%b ", cout);

end
 endmodule




Inmultire 2 numere 3 biti -> rezultat 4 biti

module XOR(a, b, w1);

  input a, b;
  output reg w1;

  always @(a or b)
  begin
    w1 = a ^ b;
  end

endmodule

module AND(c, d, w2);

  input c, d;
  output reg w2;

  always @(c or d)
  begin
    w2 = c & d;
  end
endmodule

module OR(e, f, w3);

  input e, f;
  output reg w3;

  always @(e or f)
  begin
    w3 = e | f;
  end
endmodule

module NOR(h, i, w4);
    input h, i;
    output reg w4;

    always @(h or i)
    begin
      w4 = ~(h | i);
    end
endmodule

module something(a0, a1, b0, b1, c0, c1, c2, c3);

  input a0, a1, b0, b1;
  output c0, c1, c2, c3;
  wire w1, w3, w4;
  AND and1(a0, b1, w1);
  AND and2(a0, b0, c0);
  AND and3(a1, b0, w3);
  AND and4(a1, b1, w4);
  XOR xor1(w1, w3, c1);
  AND and5(w1, w3, w5);
  XOR xor2(w5, w4, c2);
  AND And6(w4, w5, c3);

endmodule

module Testbench;
  reg a, a0, b0, b1;
  wire c0, c1, c2, c3;

 something p(a, a0, b0, b1, c0,c1,c2,c3);
 initial
  begin
   a  = 0;
   a0 = 1;
   b0 = 1;
   b1 = 1;
    #1 $display("S=%b, S=%b, S=%b, S=%b", c0, c1, c2, c3);

     a  = 1;
   a0 = 1;
   b0 = 1;
   b1 = 1;
    #1 $display("S=%b, S=%b, S=%b, S=%b", c0, c1, c2, c3);

end
 endmodule