Verilog Test File

//Registers defined (6)
// slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5

slv_reg0 = 8'h01 // Set to value 1
slv_reg1 = 8'h02 // Set to value 2
slv_reg2 = 8'h03 // Set to value 3
slv_reg3 = 8'h04 // Set to value 4

slv_reg4 = 8'h00 // Set to zero
slv_reg5 = 8'h00 // Temporary Register

always @ (posedge S_AXI_ACLK)   // Global Clock
  begin
    for (i = 0; i < 4; i = i+1) // Loop going through all slv_registers
      begin
        if (slv_reg[i] > slv_reg4) // This checks if slv_registers are greater than 0, only want to read slv_reg0-slv_reg3
          slv_reg5 = slv_reg[i]; // Set the empty temp register to the greatest value found and store it in there.

     $display("Max value is %x", slv_reg5);

      end
    end