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imx6ul-ccimx6ulstarter-wb.dts

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  1. /*
  2. * Device tree generated automatically by Digi ConnectCore Smart IOmux.
  3. *
  4. * This file is provided "AS IS" without any warranties and support, it is
  5. * just a guideline that requires additional customization.
  6. *
  7. * Please verify the calculated pin assignments with the hardware reference
  8. * manual for your platform, review the commented lines, and add the
  9. * specific values for your hardware.
  10. */
  11.  
  12. /dts-v1/;
  13.  
  14. /* i.MX6 UltraLite CPU */
  15. #include "imx6ul.dtsi"
  16. /* ConnectCore 6UL (wireless/bluetooth variant) */
  17. #include "imx6ul-ccimx6ul-wb.dtsi"
  18.  
  19. #include <dt-bindings/usb/pd.h>
  20.  
  21. / {
  22. // Add here your platform model.
  23. model = "ConnectCore 6UL";
  24. // Add here your compatible platform.
  25. compatible = "digi,ccimx6ul", "fsl,imx6ul";
  26. };
  27.  
  28. &ecspi1 {
  29. // PPTEST
  30. fsl,spi-num-chipselects = <1>;
  31. //cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  32. //num-cs = <1>;
  33. // PPTEST END
  34. pinctrl-names = "default";
  35. status = "okay";
  36.  
  37.  
  38. /*
  39. * Configure the GPIO that you selected as 'slave select'.
  40. */
  41. //cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  42.  
  43. /*
  44. * ECSPI1 (as master)
  45. */
  46. pinctrl-0 = <&pinctrl_ecspi1>;
  47.  
  48. /*
  49. * Reference block.
  50. *
  51. * Add your slave devices here. Next is an example of spidev.
  52. * Expect a harmless kernel warning if you enable spidev as slave.
  53. */
  54. spidev@0 {
  55. reg = <0>;
  56. compatible = "linux,spidev";
  57. spi-max-frequency = <1000000>;
  58. };
  59.  
  60. };
  61.  
  62. &ecspi4 {
  63. // PPTEST
  64. //fsl,spi-num-chipselects = <1>; not mentioned in iomux
  65. num-cs = <1>;
  66. cs-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
  67. // PPTEST END
  68. pinctrl-names = "default";
  69. status = "okay";
  70.  
  71. /*
  72. * Configure the GPIO that you selected as 'slave select'.
  73. */
  74. //cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  75.  
  76. /*
  77. * ECSPI4 (as master)
  78. */
  79. pinctrl-0 = <&pinctrl_ecspi4>;
  80.  
  81. /*
  82. * Reference block.
  83. *
  84. * Add your slave devices here. Next is an example of spidev.
  85. * Expect a harmless kernel warning if you enable spidev as slave.
  86. */
  87. spidev@0 {
  88. reg = <0>;
  89. compatible = "linux,spidev";
  90. spi-max-frequency = <1000000>;
  91. };
  92.  
  93. };
  94.  
  95. &fec1 {
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet_mdio>;
  98. phy-mode = "rmii";
  99. phy-handle = <&ethphy1>;
  100.  
  101. /*
  102. * Optional fields.
  103. *
  104. * Configure the PHY reset with a GPIO in your design.
  105. */
  106. //phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>
  107. //phy-reset-duration = <26>;
  108. //digi,phy-reset-in-suspend;
  109.  
  110. status = "okay";
  111.  
  112. mdio {
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115.  
  116. ethphy1: ethernet-phy@0 {
  117. compatible = "ethernet-phy-ieee802.3-c22";
  118.  
  119. /*
  120. * Add your custom PHY configuration.
  121. */
  122. //smsc,disable-energy-detect;
  123. reg = <0>;
  124. };
  125.  
  126. ethphy2: ethernet-phy@1 {
  127. compatible = "ethernet-phy-ieee802.3-c22";
  128.  
  129. /*
  130. * Add your custom PHY configuration.
  131. */
  132. //smsc,disable-energy-detect;
  133. reg = <1>;
  134. };
  135. };
  136. };
  137.  
  138. // See imx6ul-14x14-evk-ecspi.dts
  139. &fec2 {
  140. status = "disabled";
  141. };
  142.  
  143. &i2c3 {
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&pinctrl_i2c3>;
  146. //pinctrl-1 = <&pinctrl_i2c3_gpio>;
  147. //clock-frequency = <100000>;
  148.  
  149. /* Uncomment and fill with your current scl/sda lines. */
  150. //scl-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
  151. //sda-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
  152. //From arm/boot/dts/imx6ull-colibri.dtsi
  153. //sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  154. //scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  155. // IOmux does not permit the reuse of GPIO pins
  156. // i2c3 is ALT3 and GPIO is ALT5
  157. // Present in imx6ull-colibri.dtsi for i2c2 but nowhere else
  158. /*
  159. scl-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  160. sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  161. */
  162. status = "okay";
  163.  
  164. /*
  165. * Reference block.
  166. *
  167. * Add the peripherals connected to the I2C.
  168. */
  169. ptn5110: tcpc@50 {
  170. compatible = "nxp,ptn5110";
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&pinctrl_typec>;
  173. reg = <0x50>;
  174. // Already connected to USB_OTG_ID
  175. interrupt-parent = <&gpio1>;
  176. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  177. // Give this a try then try 400000
  178. clock-frequency = <400000>;
  179. status = "okay";
  180.  
  181. usb_con: connector {
  182. compatible = "usb-c-connector";
  183. label = "USB-C";
  184. power-role = "dual";
  185. data-role = "dual";
  186. try-power-role = "sink";
  187. source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  188. sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
  189. PDO_VAR(5000, 20000, 3000)>;
  190. op-sink-microwatt = <15000000>;
  191. self-powered;
  192. };
  193.  
  194. };
  195. };
  196.  
  197. &uart2 {
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_uart2>;
  200.  
  201. uart-has-rtscts;
  202.  
  203. status = "okay";
  204. };
  205.  
  206. &uart5 {
  207. pinctrl-names = "default";
  208. pinctrl-0 = <&pinctrl_console>;
  209. status = "okay";
  210. };
  211.  
  212. &usbotg1 {
  213. dr_mode = "otg";
  214.  
  215. /* Set the proper voltage regulator. */
  216. //vbus-supply = <&reg_usb_otg1_vbus>;
  217.  
  218. /*
  219. * Configure the power line if needed.
  220. */
  221. //digi,power-line-active-high;
  222.  
  223. /*
  224. * Configure the overcurrent line if needed.
  225. */
  226. //disable-over-current;
  227.  
  228. pinctrl-0 = <&pinctrl_usbotg1>;
  229.  
  230. status = "okay";
  231. };
  232.  
  233. &usdhc2 {
  234. pinctrl-names = "default";
  235. pinctrl-0 = <&pinctrl_usdhc2>;
  236. broken-cd; /* no carrier detect line (use polling) */
  237. no-1-8-v;
  238. status = "okay";
  239. };
  240.  
  241. &iomuxc {
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_hog>;
  244.  
  245. imx6ul-ccimx6ul {
  246. pinctrl_console: uart5grp {
  247. fsl,pins = <
  248. MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
  249. MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
  250. >;
  251. };
  252.  
  253. pinctrl_typec: typecgrp {
  254. fsl,pins = <
  255. /* PTN5110 irq line (ALERT) from ccimx8x-sbc-pro.dtsi */
  256. //IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000021 original
  257. // This is incorrect
  258. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  259. // OTG1 tied low
  260. //MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059
  261. >;
  262. };
  263.  
  264. pinctrl_ecspi1: ecspi1grp1 {
  265. fsl,pins = <
  266. MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
  267. MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
  268. MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
  269. // PPTEST chip select Y2/CSI_DATA5 on schematic
  270. MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x10b0 /* Chip Select */
  271. >;
  272. };
  273.  
  274. pinctrl_ecspi4: ecspi4grp1 {
  275. fsl,pins = <
  276. MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0
  277. MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0
  278. MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0
  279. // PPTEST chip select C15/NAND_DATA7 on schematic
  280. //MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x10b0 /* Chip Select */
  281. // Milen has opted to use R1
  282. MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* Chip Select */
  283. >;
  284. };
  285.  
  286. pinctrl_enet1: enet1grp {
  287. fsl,pins = <
  288. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  289. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  290. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  291. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  292. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  293. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  294. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
  295. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  296. >;
  297. };
  298.  
  299. pinctrl_enet_mdio: mdioenetgrp {
  300. fsl,pins = <
  301. MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
  302. MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
  303. >;
  304. };
  305.  
  306. pinctrl_hog: hoggrp {
  307. fsl,pins = <
  308. /* ENET1_INT# */
  309. MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x10b0
  310. /* SPI4_SS0 */
  311. // Already mentioned in ecspi4
  312. //MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0
  313. /* SPI1_IRQ_N */
  314. MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x10b0
  315. /* GPIO4_IO17 */
  316. MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x10b0
  317. /* GPIO2_IO11 */
  318. MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x10b0
  319. /* GPIO2_IO12 */
  320. MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x10b0
  321. /* GPIO1_IO24 */
  322. MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0
  323. /* GPIO1_IO25 */
  324. MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0
  325. /* GPIO1_IO05 */
  326. MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x10b0
  327. /* GPIO4_IO18 */
  328. MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0
  329. /* GPIO1_IO09 */
  330. MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x10b0
  331. /* GPIO1_IO27 */
  332. MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0
  333. /* INT IO */
  334. MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0
  335. /* RESET IO */
  336. MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0
  337. /* WDOG_TOG */
  338. MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x10b0
  339. /* 24V_IS_EN */
  340. MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0
  341. /* GPIO2_IO15 */
  342. MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0
  343. >;
  344. };
  345.  
  346. pinctrl_i2c3: i2c3grp {
  347. fsl,pins = <
  348. MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x4001b8b0
  349. MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x4001b8b0
  350. >;
  351. };
  352.  
  353. // IOmux does not permit reuse of the same pins
  354. /*
  355. pinctrl_i2c3_gpio: i2c3-gpio-grp {
  356. fsl,pins = <
  357. // From From arm/boot/dts/imx6ull-colibri.dtsi
  358. //MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
  359. //MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
  360. MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x4001b8b0
  361. MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x4001b8b0
  362. >;
  363. };
  364. */
  365. pinctrl_uart2: uart2grp {
  366. fsl,pins = <
  367. MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  368. MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  369. MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
  370. MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
  371. >;
  372. };
  373.  
  374. pinctrl_usbotg1: usbotg1grp {
  375. fsl,pins = <
  376. // Already using this pin as a GPIO
  377. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  378. MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
  379. MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x17059
  380. >;
  381. };
  382.  
  383. pinctrl_usdhc2: usdhc2grp {
  384. fsl,pins = <
  385. MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
  386. MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
  387. MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
  388. MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
  389. MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
  390. MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
  391. >;
  392. };
  393. };
  394. };
  395.  
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