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  1. [diego@myhost ~]$ glxgears
  2. couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable
  3. max_warps = 128, tls_size = 4096 KiB
  4. Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable
  5. MM: new slab, total memory = 512 KiB
  6. Running synchronized to the vertical refresh. The framerate should be
  7. approximately the same as the monitor refresh rate.
  8. MM: new slab, total memory = 640 KiB
  9. VERT
  10. DCL IN[0]
  11. DCL OUT[0], POSITION
  12. DCL OUT[1], COLOR
  13. DCL CONST[0..9]
  14. DCL TEMP[0..3]
  15. IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000}
  16. 0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  17. 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  18. 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  19. 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  20. 4: DP3 TEMP[1].x, CONST[4], CONST[4]
  21. 5: RSQ TEMP[1].x, TEMP[1]
  22. 6: MUL TEMP[0], CONST[4], TEMP[1].xxxx
  23. 7: MOV TEMP[2], CONST[5]
  24. 8: MOV OUT[1], TEMP[2]
  25. 9: DP3 TEMP[3], TEMP[0], CONST[6]
  26. 10: MAX TEMP[1], IMM[0].xxxy, TEMP[3]
  27. 11: SLT TEMP[1].z, IMM[0].xxxx, TEMP[3]
  28. 12: ADD TEMP[2], CONST[7], TEMP[2]
  29. 13: MAD TEMP[2], TEMP[1].yyyy, CONST[8], TEMP[2]
  30. 14: MAD OUT[1].xyz, TEMP[1].zzzz, CONST[9], TEMP[2]
  31. 15: END
  32. bld_instruction: 1: MUL TEMP[0], IN[0].xxxx, CONST[0]
  33. bld_instruction: 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  34. bld_instruction: 1: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  35. bld_instruction: 1: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  36. bld_instruction: 1: DP3 TEMP[1].x, CONST[4], CONST[4]
  37. bld_instruction: 1: RSQ TEMP[1].x, TEMP[1]
  38. bld_instruction: 1: MUL TEMP[0], CONST[4], TEMP[1].xxxx
  39. bld_instruction: 1: MOV TEMP[2], CONST[5]
  40. bld_instruction: 1: MOV OUT[1], TEMP[2]
  41. bld_instruction: 1: DP3 TEMP[3], TEMP[0], CONST[6]
  42. bld_instruction: 1: MAX TEMP[1], IMM[0].xxxy, TEMP[3]
  43. bld_instruction: 1: SLT TEMP[1].z, IMM[0].xxxx, TEMP[3]
  44. bld_instruction: 1: ADD TEMP[2], CONST[7], TEMP[2]
  45. bld_instruction: 1: MAD TEMP[2], TEMP[1].yyyy, CONST[8], TEMP[2]
  46. bld_instruction: 1: MAD OUT[1].xyz, TEMP[1].zzzz, CONST[9], TEMP[2]
  47. bld_instruction: 1: END
  48. MAIN
  49. === BB 0 ===
  50. 0: lda f32 %r1 f32 s[0x0] s
  51. 0: lda f32 %r3 f32 c0[0x0] s
  52. 0: mul f32 %r4 f32 %r1 f32 %r3 s
  53. 0: lda f32 %r6 f32 s[0x0] s
  54. 0: lda f32 %r8 f32 c0[0x4] s
  55. 0: mul f32 %r9 f32 %r6 f32 %r8 s
  56. 0: lda f32 %r11 f32 s[0x0] s
  57. 0: lda f32 %r13 f32 c0[0x8] s
  58. 0: mul f32 %r14 f32 %r11 f32 %r13 s
  59. 0: lda f32 %r16 f32 s[0x0] s
  60. 0: lda f32 %r18 f32 c0[0xc] s
  61. 0: mul f32 %r19 f32 %r16 f32 %r18 s
  62. 0: lda f32 %r21 f32 s[0x4] s
  63. 0: lda f32 %r23 f32 c0[0x10] s
  64. 0: mad f32 %r24 f32 %r21 f32 %r23 f32 %r4 s
  65. 0: lda f32 %r26 f32 s[0x4] s
  66. 0: lda f32 %r28 f32 c0[0x14] s
  67. 0: mad f32 %r29 f32 %r26 f32 %r28 f32 %r9 s
  68. 0: lda f32 %r31 f32 s[0x4] s
  69. 0: lda f32 %r33 f32 c0[0x18] s
  70. 0: mad f32 %r34 f32 %r31 f32 %r33 f32 %r14 s
  71. 0: lda f32 %r36 f32 s[0x4] s
  72. 0: lda f32 %r38 f32 c0[0x1c] s
  73. 0: mad f32 %r39 f32 %r36 f32 %r38 f32 %r19 s
  74. 0: lda f32 %r41 f32 s[0x8] s
  75. 0: lda f32 %r43 f32 c0[0x20] s
  76. 0: mad f32 %r44 f32 %r41 f32 %r43 f32 %r24 s
  77. 0: lda f32 %r46 f32 s[0x8] s
  78. 0: lda f32 %r48 f32 c0[0x24] s
  79. 0: mad f32 %r49 f32 %r46 f32 %r48 f32 %r29 s
  80. 0: lda f32 %r51 f32 s[0x8] s
  81. 0: lda f32 %r53 f32 c0[0x28] s
  82. 0: mad f32 %r54 f32 %r51 f32 %r53 f32 %r34 s
  83. 0: lda f32 %r56 f32 s[0x8] s
  84. 0: lda f32 %r58 f32 c0[0x2c] s
  85. 0: mad f32 %r59 f32 %r56 f32 %r58 f32 %r39 s
  86. 0: lda f32 %r61 f32 s[0xc] s
  87. 0: lda f32 %r63 f32 c0[0x30] s
  88. 0: mad f32 %r64 f32 %r61 f32 %r63 f32 %r44 s
  89. 0: lda f32 %r66 f32 s[0xc] s
  90. 0: lda f32 %r68 f32 c0[0x34] s
  91. 0: mad f32 %r69 f32 %r66 f32 %r68 f32 %r49 s
  92. 0: lda f32 %r71 f32 s[0xc] s
  93. 0: lda f32 %r73 f32 c0[0x38] s
  94. 0: mad f32 %r74 f32 %r71 f32 %r73 f32 %r54 s
  95. 0: lda f32 %r76 f32 s[0xc] s
  96. 0: lda f32 %r78 f32 c0[0x3c] s
  97. 0: mad f32 %r79 f32 %r76 f32 %r78 f32 %r59 s
  98. 0: mov f32 $o0 f32 %r64 s
  99. 0: mov f32 $o1 f32 %r69 s
  100. 0: mov f32 $o2 f32 %r74 s
  101. 0: mov f32 $o3 f32 %r79 s
  102. 0: lda f32 %r85 f32 c0[0x40] s
  103. 0: lda f32 %r87 f32 c0[0x40] s
  104. 0: mul f32 %r88 f32 %r85 f32 %r87 s
  105. 0: lda f32 %r90 f32 c0[0x44] s
  106. 0: lda f32 %r92 f32 c0[0x44] s
  107. 0: mad f32 %r93 f32 %r90 f32 %r92 f32 %r88 s
  108. 0: lda f32 %r95 f32 c0[0x48] s
  109. 0: lda f32 %r97 f32 c0[0x48] s
  110. 0: mad f32 %r98 f32 %r95 f32 %r97 f32 %r93 s
  111. 0: abs f32 %r99 f32 %r98 s
  112. 0: rsqrt f32 %r100 f32 %r99 s
  113. 0: lda f32 %r102 f32 c0[0x40] s
  114. 0: mul f32 %r103 f32 %r102 f32 %r100 s
  115. 0: lda f32 %r105 f32 c0[0x44] s
  116. 0: mul f32 %r106 f32 %r105 f32 %r100 s
  117. 0: lda f32 %r108 f32 c0[0x48] s
  118. 0: mul f32 %r109 f32 %r108 f32 %r100 s
  119. 0: lda f32 %r111 f32 c0[0x4c] s
  120. 0: mul f32 %r112 f32 %r111 f32 %r100 s
  121. 0: lda u32 %r114 u32 c0[0x50] s
  122. 0: lda u32 %r116 u32 c0[0x54] s
  123. 0: lda u32 %r118 u32 c0[0x58] s
  124. 0: lda u32 %r120 u32 c0[0x5c] s
  125. 0: mov u32 $o4 u32 %r114 s
  126. 0: mov u32 $o5 u32 %r116 s
  127. 0: mov u32 $o6 u32 %r118 s
  128. 0: mov u32 $o7 u32 %r120 s
  129. 0: lda f32 %r126 f32 c0[0x60] s
  130. 0: mul f32 %r127 f32 %r103 f32 %r126 s
  131. 0: lda f32 %r129 f32 c0[0x64] s
  132. 0: mad f32 %r130 f32 %r106 f32 %r129 f32 %r127 s
  133. 0: lda f32 %r132 f32 c0[0x68] s
  134. 0: mad f32 %r133 f32 %r109 f32 %r132 f32 %r130 s
  135. 0: mov f32 %r135 u32 0x00000000 s
  136. 0: max f32 %r136 f32 %r135 f32 %r133 s
  137. 0: mov f32 %r137 u32 0x00000000 s
  138. 0: max f32 %r138 f32 %r137 f32 %r133 s
  139. 0: mov f32 %r139 u32 0x00000000 s
  140. 0: max f32 %r140 f32 %r139 f32 %r133 s
  141. 0: mov f32 %r142 u32 0x3f800000 s
  142. 0: max f32 %r143 f32 %r142 f32 %r133 s
  143. 0: mov f32 %r144 u32 0x00000000 s
  144. 0: set lt f32 %r145 f32 %r144 f32 %r133 s
  145. 0: abs s32 %r146 s32 %r145 s
  146. 0: cvt f32 %r147 s32 %r146 s
  147. 0: lda f32 %r149 f32 c0[0x70] s
  148. 0: add f32 %r150 f32 %r149 f32 %r114 s
  149. 0: lda f32 %r152 f32 c0[0x74] s
  150. 0: add f32 %r153 f32 %r152 f32 %r116 s
  151. 0: lda f32 %r155 f32 c0[0x78] s
  152. 0: add f32 %r156 f32 %r155 f32 %r118 s
  153. 0: lda f32 %r158 f32 c0[0x7c] s
  154. 0: add f32 %r159 f32 %r158 f32 %r120 s
  155. 0: lda f32 %r161 f32 c0[0x80] s
  156. 0: mad f32 %r162 f32 %r138 f32 %r161 f32 %r150 s
  157. 0: lda f32 %r164 f32 c0[0x84] s
  158. 0: mad f32 %r165 f32 %r138 f32 %r164 f32 %r153 s
  159. 0: lda f32 %r167 f32 c0[0x88] s
  160. 0: mad f32 %r168 f32 %r138 f32 %r167 f32 %r156 s
  161. 0: lda f32 %r170 f32 c0[0x8c] s
  162. 0: mad f32 %r171 f32 %r138 f32 %r170 f32 %r159 s
  163. 0: lda f32 %r173 f32 c0[0x90] s
  164. 0: mad f32 %r174 f32 %r147 f32 %r173 f32 %r162 s
  165. 0: lda f32 %r176 f32 c0[0x94] s
  166. 0: mad f32 %r177 f32 %r147 f32 %r176 f32 %r165 s
  167. 0: lda f32 %r179 f32 c0[0x98] s
  168. 0: mad f32 %r180 f32 %r147 f32 %r179 f32 %r168 s
  169. 0: mov f32 $o4 f32 %r174 s
  170. 0: mov f32 $o5 f32 %r177 s
  171. 0: mov f32 $o6 f32 %r180 s
  172. MAIN
  173. === BB 0 ===
  174. 0: mul f32 %r4 f32 s[0x0] f32 c0[0x0] s
  175. 0: mul f32 %r9 f32 s[0x0] f32 c0[0x4] s
  176. 0: mul f32 %r14 f32 s[0x0] f32 c0[0x8] s
  177. 0: mul f32 %r19 f32 s[0x0] f32 c0[0xc] s
  178. 0: mad f32 %r24 f32 s[0x4] f32 c0[0x10] f32 %r4 s
  179. 0: mad f32 %r29 f32 s[0x4] f32 c0[0x14] f32 %r9 s
  180. 0: mad f32 %r34 f32 s[0x4] f32 c0[0x18] f32 %r14 s
  181. 0: mad f32 %r39 f32 s[0x4] f32 c0[0x1c] f32 %r19 s
  182. 0: mad f32 %r44 f32 s[0x8] f32 c0[0x20] f32 %r24 s
  183. 0: mad f32 %r49 f32 s[0x8] f32 c0[0x24] f32 %r29 s
  184. 0: mad f32 %r54 f32 s[0x8] f32 c0[0x28] f32 %r34 s
  185. 0: mad f32 %r59 f32 s[0x8] f32 c0[0x2c] f32 %r39 s
  186. 0: mad f32 $o0 f32 s[0xc] f32 c0[0x30] f32 %r44 s
  187. 0: mad f32 $o1 f32 s[0xc] f32 c0[0x34] f32 %r49 s
  188. 0: mad f32 $o2 f32 s[0xc] f32 c0[0x38] f32 %r54 s
  189. 0: mad f32 $o3 f32 s[0xc] f32 c0[0x3c] f32 %r59 s
  190. 0: lda f32 %r85 f32 c0[0x40] s
  191. 0: mul f32 %r88 f32 %r85 f32 c0[0x40] s
  192. 0: lda f32 %r90 f32 c0[0x44] s
  193. 0: mad f32 %r93 f32 %r90 f32 c0[0x44] f32 %r88 s
  194. 0: lda f32 %r95 f32 c0[0x48] s
  195. 0: mad f32 %r98 f32 %r95 f32 c0[0x48] f32 %r93 s
  196. 0: rsqrt f32 %r100 abs f32 %r98 s
  197. 0: mul f32 %r103 f32 %r100 f32 c0[0x40] s
  198. 0: mul f32 %r106 f32 %r100 f32 c0[0x44] s
  199. 0: mul f32 %r109 f32 %r100 f32 c0[0x48] s
  200. 0: lda u32 $o4 u32 c0[0x50] s
  201. 0: lda u32 $o5 u32 c0[0x54] s
  202. 0: lda u32 $o6 u32 c0[0x58] s
  203. 0: lda u32 $o7 u32 c0[0x5c] s
  204. 0: mul f32 %r127 f32 %r103 f32 c0[0x60] s
  205. 0: mad f32 %r130 f32 %r106 f32 c0[0x64] f32 %r127 s
  206. 0: mad f32 %r133 f32 %r109 f32 c0[0x68] f32 %r130 s
  207. 0: mov f32 %r135 u32 0x00000000 s
  208. 0: max f32 %r136 f32 %r135 f32 %r133 s
  209. 0: set lt f32 %r145 f32 %r135 f32 %r133 s
  210. 0: cvt f32 %r147 abs s32 %r145 s
  211. 0: lda f32 %r149 f32 c0[0x70] s
  212. 0: add f32 %r150 f32 %r149 f32 c0[0x50] s
  213. 0: lda f32 %r152 f32 c0[0x74] s
  214. 0: add f32 %r153 f32 %r152 f32 c0[0x54] s
  215. 0: lda f32 %r155 f32 c0[0x78] s
  216. 0: add f32 %r156 f32 %r155 f32 c0[0x58] s
  217. 0: mad f32 %r162 f32 %r136 f32 c0[0x80] f32 %r150 s
  218. 0: mad f32 %r165 f32 %r136 f32 c0[0x84] f32 %r153 s
  219. 0: mad f32 %r168 f32 %r136 f32 c0[0x88] f32 %r156 s
  220. 0: mad f32 $o4 f32 %r147 f32 c0[0x90] f32 %r162 s
  221. 0: mad f32 $o5 f32 %r147 f32 c0[0x94] f32 %r165 s
  222. 0: mad f32 $o6 f32 %r147 f32 c0[0x98] f32 %r168 s
  223. REGISTER ALLOCATION - entering
  224. REGISTER ALLOCATION - leaving
  225. MAIN
  226. === BB 0 ===
  227. 0: mul f32 $r0 f32 s[0x0] f32 c0[0x0] s
  228. 1: mul f32 $r1 f32 s[0x0] f32 c0[0x4] s
  229. 2: mul f32 $r2 f32 s[0x0] f32 c0[0x8] s
  230. 3: mul f32 $r3 f32 s[0x0] f32 c0[0xc] s
  231. 4: mad f32 $r0 f32 s[0x4] f32 c0[0x10] f32 $r0 s
  232. 5: mad f32 $r1 f32 s[0x4] f32 c0[0x14] f32 $r1 s
  233. 6: mad f32 $r2 f32 s[0x4] f32 c0[0x18] f32 $r2 s
  234. 7: mad f32 $r3 f32 s[0x4] f32 c0[0x1c] f32 $r3 s
  235. 8: mad f32 $r0 f32 s[0x8] f32 c0[0x20] f32 $r0 s
  236. 9: mad f32 $r1 f32 s[0x8] f32 c0[0x24] f32 $r1 s
  237. 10: mad f32 $r2 f32 s[0x8] f32 c0[0x28] f32 $r2 s
  238. 11: mad f32 $r3 f32 s[0x8] f32 c0[0x2c] f32 $r3 s
  239. 12: mad f32 $o0 f32 s[0xc] f32 c0[0x30] f32 $r0 s
  240. 13: mad f32 $o1 f32 s[0xc] f32 c0[0x34] f32 $r1 s
  241. 14: mad f32 $o2 f32 s[0xc] f32 c0[0x38] f32 $r2 s
  242. 15: mad f32 $o3 f32 s[0xc] f32 c0[0x3c] f32 $r3 s
  243. 16: lda f32 $r0 f32 c0[0x40] s
  244. 17: mul f32 $r0 f32 $r0 f32 c0[0x40] s
  245. 18: lda f32 $r1 f32 c0[0x44] s
  246. 19: mad f32 $r0 f32 $r1 f32 c0[0x44] f32 $r0 s
  247. 20: lda f32 $r1 f32 c0[0x48] s
  248. 21: mad f32 $r0 f32 $r1 f32 c0[0x48] f32 $r0 s
  249. 22: rsqrt f32 $r0 abs f32 $r0 s
  250. 23: mul f32 $r1 f32 $r0 f32 c0[0x40] s
  251. 24: mul f32 $r2 f32 $r0 f32 c0[0x44] s
  252. 25: mul f32 $r0 f32 $r0 f32 c0[0x48] s
  253. 26: lda u32 $o4 u32 c0[0x50] s
  254. 27: lda u32 $o5 u32 c0[0x54] s
  255. 28: lda u32 $o6 u32 c0[0x58] s
  256. 29: lda u32 $o7 u32 c0[0x5c] s
  257. 30: mul f32 $r1 f32 $r1 f32 c0[0x60] s
  258. 31: mad f32 $r1 f32 $r2 f32 c0[0x64] f32 $r1 s
  259. 32: mad f32 $r0 f32 $r0 f32 c0[0x68] f32 $r1 s
  260. 33: mov f32 $r1 u32 0x00000000 s
  261. 34: max f32 $r2 f32 $r1 f32 $r0 s
  262. 35: set lt f32 $r0 f32 $r1 f32 $r0 s
  263. 36: cvt f32 $r0 abs s32 $r0 s
  264. 37: lda f32 $r1 f32 c0[0x70] s
  265. 38: add f32 $r1 f32 $r1 f32 c0[0x50] s
  266. 39: lda f32 $r3 f32 c0[0x74] s
  267. 40: add f32 $r3 f32 $r3 f32 c0[0x54] s
  268. 41: lda f32 $r4 f32 c0[0x78] s
  269. 42: add f32 $r4 f32 $r4 f32 c0[0x58] s
  270. 43: mad f32 $r1 f32 $r2 f32 c0[0x80] f32 $r1 s
  271. 44: mad f32 $r3 f32 $r2 f32 c0[0x84] f32 $r3 s
  272. 45: mad f32 $r2 f32 $r2 f32 c0[0x88] f32 $r4 s
  273. 46: mad f32 $o4 f32 $r0 f32 c0[0x90] f32 $r1 s
  274. 47: mad f32 $o5 f32 $r0 f32 c0[0x94] f32 $r3 s
  275. 48: mad f32 $o6 f32 $r0 f32 c0[0x98] f32 $r2 s
  276. preparing 1 blocks for emission
  277. emitting program: size = 392
  278. 0xc0800001 0x00200780 0xc0810005 0x00200780 0xc0820009 0x00200780 0xc083000d 0x00200780 0xe0840201 0x00200780 0xe0850205 0x00204780 0xe0860209 0x00208780 0xe087020d 0x0020c780
  279. 0xe0880401 0x00200780 0xe0890405 0x00204780 0xe08a0409 0x00208780 0xe08b040d 0x0020c780 0xe08c0601 0x00200788 0xe08d0605 0x00204788 0xe08e0609 0x00208788 0xe08f060d 0x0020c788
  280. 0x10002001 0x2400c780 0xc0900001 0x00000780 0x10002205 0x2400c780 0xe0910201 0x00000780 0x10002405 0x2400c780 0xe0920201 0x00000780 0x90000001 0x40100780 0xc0900005 0x00000780
  281. 0xc0910009 0x00000780 0xc0920001 0x00000780 0x10002811 0x2400c788 0x10002a15 0x2400c788 0x10002c19 0x2400c788 0x10002e1d 0x2400c788 0xc0980205 0x00000780 0xe0990405 0x00004780
  282. 0xe09a0001 0x00004780 0x10008005 0x00000003 0xb0000209 0x80000780 0xb0000201 0x60004780 0xa0000001 0x44114780 0x10003805 0x2400c780 0xb1000205 0x00050780 0x10003a0d 0x2400c780
  283. 0xb100060d 0x00054780 0x10003c11 0x2400c780 0xb1000811 0x00058780 0xe0a00405 0x00004780 0xe0a1040d 0x0000c780 0xe0a20409 0x00010780 0xe0a40011 0x00004788 0xe0a50015 0x0000c788
  284. 0xe0a60019 0x00008789
  285. SHADER TRANSLATION - success
  286. Uploading code to offset 0007fe00, len 392
  287. FRAG
  288. PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
  289. DCL IN[0], COLOR, LINEAR
  290. DCL OUT[0], COLOR
  291. 0: MOV OUT[0], IN[0]
  292. 1: END
  293. bld_instruction: 1: MOV OUT[0], IN[0]
  294. bld_instruction: 1: END
  295. MAIN
  296. === BB 0 ===
  297. 0: linterp f32 %r1 f32 v[0x0] s
  298. 0: rcp f32 %r2 f32 %r1 s
  299. 0: linterp u32 %r4 u32 v[0x4] s
  300. 0: linterp u32 %r6 u32 v[0x8] s
  301. 0: linterp u32 %r8 u32 v[0xc] s
  302. 0: linterp u32 %r10 u32 v[0x10] s
  303. 0: mov u32 %r11 u32 %r4 s
  304. 0: mov u32 %r12 u32 %r6 s
  305. 0: mov u32 %r13 u32 %r8 s
  306. 0: mov u32 %r14 u32 %r10 s
  307. 0: mov u32 $r0 u32 %r11 s
  308. 0: mov u32 $r1 u32 %r12 s
  309. 0: mov u32 $r2 u32 %r13 s
  310. 0: mov u32 $r3 u32 %r14 s
  311. 0: export # u32 $r0 u32 $r1 u32 $r2 u32 $r3 s
  312. MAIN
  313. === BB 0 ===
  314. 0: linterp u32 %r4 u32 v[0x4] s
  315. 0: linterp u32 %r6 u32 v[0x8] s
  316. 0: linterp u32 %r8 u32 v[0xc] s
  317. 0: linterp u32 %r10 u32 v[0x10] s
  318. 0: mov u32 %r11 u32 %r4 s
  319. 0: mov u32 %r12 u32 %r6 s
  320. 0: mov u32 %r13 u32 %r8 s
  321. 0: mov u32 %r14 u32 %r10 s
  322. 0: mov u32 $r0 u32 %r11 s
  323. 0: mov u32 $r1 u32 %r12 s
  324. 0: mov u32 $r2 u32 %r13 s
  325. 0: mov u32 $r3 u32 %r14 s
  326. 0: export # u32 $r0 u32 $r1 u32 $r2 u32 $r3 s
  327. REGISTER ALLOCATION - entering
  328. REGISTER ALLOCATION - leaving
  329. MAIN
  330. === BB 0 ===
  331. 0: linterp u32 $r0 u32 v[0x4] s
  332. 1: linterp u32 $r1 u32 v[0x8] s
  333. 2: linterp u32 $r2 u32 v[0xc] s
  334. 3: linterp u32 $r3 u32 v[0x10] s
  335. 4: mov u32 $r0 u32 $r0 s
  336. 5: mov u32 $r1 u32 $r1 s
  337. 6: mov u32 $r2 u32 $r2 s
  338. 7: mov u32 $r3 u32 $r3 s
  339. 8: mov u32 $r0 u32 $r0 s
  340. 9: mov u32 $r1 u32 $r1 s
  341. 10: mov u32 $r2 u32 $r2 s
  342. 11: mov u32 $r3 u32 $r3 s
  343. 12: export # u32 $r0 u32 $r1 u32 $r2 u32 $r3 s
  344. preparing 1 blocks for emission
  345. emitting program: size = 24
  346. 0x80010000 0x80020004 0x80030009 0x00000780 0x8004000d 0x00000781
  347. SHADER TRANSLATION - success
  348. Uploading code to offset 000fff00, len 24
  349. VERT
  350. DCL IN[0]
  351. DCL IN[1]
  352. DCL OUT[0], POSITION
  353. DCL OUT[1], COLOR
  354. DCL CONST[0..8]
  355. DCL TEMP[0..3]
  356. IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000}
  357. 0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  358. 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  359. 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  360. 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  361. 4: DP3 TEMP[1].x, IN[1], IN[1]
  362. 5: RSQ TEMP[1].x, TEMP[1]
  363. 6: MUL TEMP[0], IN[1], TEMP[1].xxxx
  364. 7: MOV TEMP[2], CONST[4]
  365. 8: MOV OUT[1], TEMP[2]
  366. 9: DP3 TEMP[3], TEMP[0], CONST[5]
  367. 10: MAX TEMP[1], IMM[0].xxxy, TEMP[3]
  368. 11: SLT TEMP[1].z, IMM[0].xxxx, TEMP[3]
  369. 12: ADD TEMP[2], CONST[6], TEMP[2]
  370. 13: MAD TEMP[2], TEMP[1].yyyy, CONST[7], TEMP[2]
  371. 14: MAD OUT[1].xyz, TEMP[1].zzzz, CONST[8], TEMP[2]
  372. 15: END
  373. bld_instruction: 1: MUL TEMP[0], IN[0].xxxx, CONST[0]
  374. bld_instruction: 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  375. bld_instruction: 1: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  376. bld_instruction: 1: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  377. bld_instruction: 1: DP3 TEMP[1].x, IN[1], IN[1]
  378. bld_instruction: 1: RSQ TEMP[1].x, TEMP[1]
  379. bld_instruction: 1: MUL TEMP[0], IN[1], TEMP[1].xxxx
  380. bld_instruction: 1: MOV TEMP[2], CONST[4]
  381. bld_instruction: 1: MOV OUT[1], TEMP[2]
  382. bld_instruction: 1: DP3 TEMP[3], TEMP[0], CONST[5]
  383. bld_instruction: 1: MAX TEMP[1], IMM[0].xxxy, TEMP[3]
  384. bld_instruction: 1: SLT TEMP[1].z, IMM[0].xxxx, TEMP[3]
  385. bld_instruction: 1: ADD TEMP[2], CONST[6], TEMP[2]
  386. bld_instruction: 1: MAD TEMP[2], TEMP[1].yyyy, CONST[7], TEMP[2]
  387. bld_instruction: 1: MAD OUT[1].xyz, TEMP[1].zzzz, CONST[8], TEMP[2]
  388. bld_instruction: 1: END
  389. MAIN
  390. === BB 0 ===
  391. 0: lda f32 %r1 f32 s[0x0] s
  392. 0: lda f32 %r3 f32 c0[0x0] s
  393. 0: mul f32 %r4 f32 %r1 f32 %r3 s
  394. 0: lda f32 %r6 f32 s[0x0] s
  395. 0: lda f32 %r8 f32 c0[0x4] s
  396. 0: mul f32 %r9 f32 %r6 f32 %r8 s
  397. 0: lda f32 %r11 f32 s[0x0] s
  398. 0: lda f32 %r13 f32 c0[0x8] s
  399. 0: mul f32 %r14 f32 %r11 f32 %r13 s
  400. 0: lda f32 %r16 f32 s[0x0] s
  401. 0: lda f32 %r18 f32 c0[0xc] s
  402. 0: mul f32 %r19 f32 %r16 f32 %r18 s
  403. 0: lda f32 %r21 f32 s[0x4] s
  404. 0: lda f32 %r23 f32 c0[0x10] s
  405. 0: mad f32 %r24 f32 %r21 f32 %r23 f32 %r4 s
  406. 0: lda f32 %r26 f32 s[0x4] s
  407. 0: lda f32 %r28 f32 c0[0x14] s
  408. 0: mad f32 %r29 f32 %r26 f32 %r28 f32 %r9 s
  409. 0: lda f32 %r31 f32 s[0x4] s
  410. 0: lda f32 %r33 f32 c0[0x18] s
  411. 0: mad f32 %r34 f32 %r31 f32 %r33 f32 %r14 s
  412. 0: lda f32 %r36 f32 s[0x4] s
  413. 0: lda f32 %r38 f32 c0[0x1c] s
  414. 0: mad f32 %r39 f32 %r36 f32 %r38 f32 %r19 s
  415. 0: lda f32 %r41 f32 s[0x8] s
  416. 0: lda f32 %r43 f32 c0[0x20] s
  417. 0: mad f32 %r44 f32 %r41 f32 %r43 f32 %r24 s
  418. 0: lda f32 %r46 f32 s[0x8] s
  419. 0: lda f32 %r48 f32 c0[0x24] s
  420. 0: mad f32 %r49 f32 %r46 f32 %r48 f32 %r29 s
  421. 0: lda f32 %r51 f32 s[0x8] s
  422. 0: lda f32 %r53 f32 c0[0x28] s
  423. 0: mad f32 %r54 f32 %r51 f32 %r53 f32 %r34 s
  424. 0: lda f32 %r56 f32 s[0x8] s
  425. 0: lda f32 %r58 f32 c0[0x2c] s
  426. 0: mad f32 %r59 f32 %r56 f32 %r58 f32 %r39 s
  427. 0: lda f32 %r61 f32 s[0xc] s
  428. 0: lda f32 %r63 f32 c0[0x30] s
  429. 0: mad f32 %r64 f32 %r61 f32 %r63 f32 %r44 s
  430. 0: lda f32 %r66 f32 s[0xc] s
  431. 0: lda f32 %r68 f32 c0[0x34] s
  432. 0: mad f32 %r69 f32 %r66 f32 %r68 f32 %r49 s
  433. 0: lda f32 %r71 f32 s[0xc] s
  434. 0: lda f32 %r73 f32 c0[0x38] s
  435. 0: mad f32 %r74 f32 %r71 f32 %r73 f32 %r54 s
  436. 0: lda f32 %r76 f32 s[0xc] s
  437. 0: lda f32 %r78 f32 c0[0x3c] s
  438. 0: mad f32 %r79 f32 %r76 f32 %r78 f32 %r59 s
  439. 0: mov f32 $o0 f32 %r64 s
  440. 0: mov f32 $o1 f32 %r69 s
  441. 0: mov f32 $o2 f32 %r74 s
  442. 0: mov f32 $o3 f32 %r79 s
  443. 0: lda f32 %r85 f32 s[0x10] s
  444. 0: lda f32 %r87 f32 s[0x10] s
  445. 0: mul f32 %r88 f32 %r85 f32 %r87 s
  446. 0: lda f32 %r90 f32 s[0x14] s
  447. 0: lda f32 %r92 f32 s[0x14] s
  448. 0: mad f32 %r93 f32 %r90 f32 %r92 f32 %r88 s
  449. 0: lda f32 %r95 f32 s[0x18] s
  450. 0: lda f32 %r97 f32 s[0x18] s
  451. 0: mad f32 %r98 f32 %r95 f32 %r97 f32 %r93 s
  452. 0: abs f32 %r99 f32 %r98 s
  453. 0: rsqrt f32 %r100 f32 %r99 s
  454. 0: lda f32 %r102 f32 s[0x10] s
  455. 0: mul f32 %r103 f32 %r102 f32 %r100 s
  456. 0: lda f32 %r105 f32 s[0x14] s
  457. 0: mul f32 %r106 f32 %r105 f32 %r100 s
  458. 0: lda f32 %r108 f32 s[0x18] s
  459. 0: mul f32 %r109 f32 %r108 f32 %r100 s
  460. 0: lda f32 %r111 f32 s[0x1c] s
  461. 0: mul f32 %r112 f32 %r111 f32 %r100 s
  462. 0: lda u32 %r114 u32 c0[0x40] s
  463. 0: lda u32 %r116 u32 c0[0x44] s
  464. 0: lda u32 %r118 u32 c0[0x48] s
  465. 0: lda u32 %r120 u32 c0[0x4c] s
  466. 0: mov u32 $o4 u32 %r114 s
  467. 0: mov u32 $o5 u32 %r116 s
  468. 0: mov u32 $o6 u32 %r118 s
  469. 0: mov u32 $o7 u32 %r120 s
  470. 0: lda f32 %r126 f32 c0[0x50] s
  471. 0: mul f32 %r127 f32 %r103 f32 %r126 s
  472. 0: lda f32 %r129 f32 c0[0x54] s
  473. 0: mad f32 %r130 f32 %r106 f32 %r129 f32 %r127 s
  474. 0: lda f32 %r132 f32 c0[0x58] s
  475. 0: mad f32 %r133 f32 %r109 f32 %r132 f32 %r130 s
  476. 0: mov f32 %r135 u32 0x00000000 s
  477. 0: max f32 %r136 f32 %r135 f32 %r133 s
  478. 0: mov f32 %r137 u32 0x00000000 s
  479. 0: max f32 %r138 f32 %r137 f32 %r133 s
  480. 0: mov f32 %r139 u32 0x00000000 s
  481. 0: max f32 %r140 f32 %r139 f32 %r133 s
  482. 0: mov f32 %r142 u32 0x3f800000 s
  483. 0: max f32 %r143 f32 %r142 f32 %r133 s
  484. 0: mov f32 %r144 u32 0x00000000 s
  485. 0: set lt f32 %r145 f32 %r144 f32 %r133 s
  486. 0: abs s32 %r146 s32 %r145 s
  487. 0: cvt f32 %r147 s32 %r146 s
  488. 0: lda f32 %r149 f32 c0[0x60] s
  489. 0: add f32 %r150 f32 %r149 f32 %r114 s
  490. 0: lda f32 %r152 f32 c0[0x64] s
  491. 0: add f32 %r153 f32 %r152 f32 %r116 s
  492. 0: lda f32 %r155 f32 c0[0x68] s
  493. 0: add f32 %r156 f32 %r155 f32 %r118 s
  494. 0: lda f32 %r158 f32 c0[0x6c] s
  495. 0: add f32 %r159 f32 %r158 f32 %r120 s
  496. 0: lda f32 %r161 f32 c0[0x70] s
  497. 0: mad f32 %r162 f32 %r138 f32 %r161 f32 %r150 s
  498. 0: lda f32 %r164 f32 c0[0x74] s
  499. 0: mad f32 %r165 f32 %r138 f32 %r164 f32 %r153 s
  500. 0: lda f32 %r167 f32 c0[0x78] s
  501. 0: mad f32 %r168 f32 %r138 f32 %r167 f32 %r156 s
  502. 0: lda f32 %r170 f32 c0[0x7c] s
  503. 0: mad f32 %r171 f32 %r138 f32 %r170 f32 %r159 s
  504. 0: lda f32 %r173 f32 c0[0x80] s
  505. 0: mad f32 %r174 f32 %r147 f32 %r173 f32 %r162 s
  506. 0: lda f32 %r176 f32 c0[0x84] s
  507. 0: mad f32 %r177 f32 %r147 f32 %r176 f32 %r165 s
  508. 0: lda f32 %r179 f32 c0[0x88] s
  509. 0: mad f32 %r180 f32 %r147 f32 %r179 f32 %r168 s
  510. 0: mov f32 $o4 f32 %r174 s
  511. 0: mov f32 $o5 f32 %r177 s
  512. 0: mov f32 $o6 f32 %r180 s
  513. MAIN
  514. === BB 0 ===
  515. 0: mul f32 %r4 f32 s[0x0] f32 c0[0x0] s
  516. 0: mul f32 %r9 f32 s[0x0] f32 c0[0x4] s
  517. 0: mul f32 %r14 f32 s[0x0] f32 c0[0x8] s
  518. 0: mul f32 %r19 f32 s[0x0] f32 c0[0xc] s
  519. 0: mad f32 %r24 f32 s[0x4] f32 c0[0x10] f32 %r4 s
  520. 0: mad f32 %r29 f32 s[0x4] f32 c0[0x14] f32 %r9 s
  521. 0: mad f32 %r34 f32 s[0x4] f32 c0[0x18] f32 %r14 s
  522. 0: mad f32 %r39 f32 s[0x4] f32 c0[0x1c] f32 %r19 s
  523. 0: mad f32 %r44 f32 s[0x8] f32 c0[0x20] f32 %r24 s
  524. 0: mad f32 %r49 f32 s[0x8] f32 c0[0x24] f32 %r29 s
  525. 0: mad f32 %r54 f32 s[0x8] f32 c0[0x28] f32 %r34 s
  526. 0: mad f32 %r59 f32 s[0x8] f32 c0[0x2c] f32 %r39 s
  527. 0: mad f32 $o0 f32 s[0xc] f32 c0[0x30] f32 %r44 s
  528. 0: mad f32 $o1 f32 s[0xc] f32 c0[0x34] f32 %r49 s
  529. 0: mad f32 $o2 f32 s[0xc] f32 c0[0x38] f32 %r54 s
  530. 0: mad f32 $o3 f32 s[0xc] f32 c0[0x3c] f32 %r59 s
  531. 0: lda f32 %r87 f32 s[0x10] s
  532. 0: mul f32 %r88 f32 s[0x10] f32 %r87 s
  533. 0: lda f32 %r92 f32 s[0x14] s
  534. 0: mad f32 %r93 f32 s[0x14] f32 %r92 f32 %r88 s
  535. 0: lda f32 %r97 f32 s[0x18] s
  536. 0: mad f32 %r98 f32 s[0x18] f32 %r97 f32 %r93 s
  537. 0: rsqrt f32 %r100 abs f32 %r98 s
  538. 0: mul f32 %r103 f32 s[0x10] f32 %r100 s
  539. 0: mul f32 %r106 f32 s[0x14] f32 %r100 s
  540. 0: mul f32 %r109 f32 s[0x18] f32 %r100 s
  541. 0: lda u32 $o4 u32 c0[0x40] s
  542. 0: lda u32 $o5 u32 c0[0x44] s
  543. 0: lda u32 $o6 u32 c0[0x48] s
  544. 0: lda u32 $o7 u32 c0[0x4c] s
  545. 0: mul f32 %r127 f32 %r103 f32 c0[0x50] s
  546. 0: mad f32 %r130 f32 %r106 f32 c0[0x54] f32 %r127 s
  547. 0: mad f32 %r133 f32 %r109 f32 c0[0x58] f32 %r130 s
  548. 0: mov f32 %r135 u32 0x00000000 s
  549. 0: max f32 %r136 f32 %r135 f32 %r133 s
  550. 0: set lt f32 %r145 f32 %r135 f32 %r133 s
  551. 0: cvt f32 %r147 abs s32 %r145 s
  552. 0: lda f32 %r149 f32 c0[0x60] s
  553. 0: add f32 %r150 f32 %r149 f32 c0[0x40] s
  554. 0: lda f32 %r152 f32 c0[0x64] s
  555. 0: add f32 %r153 f32 %r152 f32 c0[0x44] s
  556. 0: lda f32 %r155 f32 c0[0x68] s
  557. 0: add f32 %r156 f32 %r155 f32 c0[0x48] s
  558. 0: mad f32 %r162 f32 %r136 f32 c0[0x70] f32 %r150 s
  559. 0: mad f32 %r165 f32 %r136 f32 c0[0x74] f32 %r153 s
  560. 0: mad f32 %r168 f32 %r136 f32 c0[0x78] f32 %r156 s
  561. 0: mad f32 $o4 f32 %r147 f32 c0[0x80] f32 %r162 s
  562. 0: mad f32 $o5 f32 %r147 f32 c0[0x84] f32 %r165 s
  563. 0: mad f32 $o6 f32 %r147 f32 c0[0x88] f32 %r168 s
  564. REGISTER ALLOCATION - entering
  565. REGISTER ALLOCATION - leaving
  566. MAIN
  567. === BB 0 ===
  568. 0: mul f32 $r0 f32 s[0x0] f32 c0[0x0] s
  569. 1: mul f32 $r1 f32 s[0x0] f32 c0[0x4] s
  570. 2: mul f32 $r2 f32 s[0x0] f32 c0[0x8] s
  571. 3: mul f32 $r3 f32 s[0x0] f32 c0[0xc] s
  572. 4: mad f32 $r0 f32 s[0x4] f32 c0[0x10] f32 $r0 s
  573. 5: mad f32 $r1 f32 s[0x4] f32 c0[0x14] f32 $r1 s
  574. 6: mad f32 $r2 f32 s[0x4] f32 c0[0x18] f32 $r2 s
  575. 7: mad f32 $r3 f32 s[0x4] f32 c0[0x1c] f32 $r3 s
  576. 8: mad f32 $r0 f32 s[0x8] f32 c0[0x20] f32 $r0 s
  577. 9: mad f32 $r1 f32 s[0x8] f32 c0[0x24] f32 $r1 s
  578. 10: mad f32 $r2 f32 s[0x8] f32 c0[0x28] f32 $r2 s
  579. 11: mad f32 $r3 f32 s[0x8] f32 c0[0x2c] f32 $r3 s
  580. 12: mad f32 $o0 f32 s[0xc] f32 c0[0x30] f32 $r0 s
  581. 13: mad f32 $o1 f32 s[0xc] f32 c0[0x34] f32 $r1 s
  582. 14: mad f32 $o2 f32 s[0xc] f32 c0[0x38] f32 $r2 s
  583. 15: mad f32 $o3 f32 s[0xc] f32 c0[0x3c] f32 $r3 s
  584. 16: lda f32 $r0 f32 s[0x10] s
  585. 17: mul f32 $r0 f32 s[0x10] f32 $r0 s
  586. 18: lda f32 $r1 f32 s[0x14] s
  587. 19: mad f32 $r0 f32 s[0x14] f32 $r1 f32 $r0 s
  588. 20: lda f32 $r1 f32 s[0x18] s
  589. 21: mad f32 $r0 f32 s[0x18] f32 $r1 f32 $r0 s
  590. 22: rsqrt f32 $r0 abs f32 $r0 s
  591. 23: mul f32 $r1 f32 s[0x10] f32 $r0 s
  592. 24: mul f32 $r2 f32 s[0x14] f32 $r0 s
  593. 25: mul f32 $r0 f32 s[0x18] f32 $r0 s
  594. 26: lda u32 $o4 u32 c0[0x40] s
  595. 27: lda u32 $o5 u32 c0[0x44] s
  596. 28: lda u32 $o6 u32 c0[0x48] s
  597. 29: lda u32 $o7 u32 c0[0x4c] s
  598. 30: mul f32 $r1 f32 $r1 f32 c0[0x50] s
  599. 31: mad f32 $r1 f32 $r2 f32 c0[0x54] f32 $r1 s
  600. 32: mad f32 $r0 f32 $r0 f32 c0[0x58] f32 $r1 s
  601. 33: mov f32 $r1 u32 0x00000000 s
  602. 34: max f32 $r2 f32 $r1 f32 $r0 s
  603. 35: set lt f32 $r0 f32 $r1 f32 $r0 s
  604. 36: cvt f32 $r0 abs s32 $r0 s
  605. 37: lda f32 $r1 f32 c0[0x60] s
  606. 38: add f32 $r1 f32 $r1 f32 c0[0x40] s
  607. 39: lda f32 $r3 f32 c0[0x64] s
  608. 40: add f32 $r3 f32 $r3 f32 c0[0x44] s
  609. 41: lda f32 $r4 f32 c0[0x68] s
  610. 42: add f32 $r4 f32 $r4 f32 c0[0x48] s
  611. 43: mad f32 $r1 f32 $r2 f32 c0[0x70] f32 $r1 s
  612. 44: mad f32 $r3 f32 $r2 f32 c0[0x74] f32 $r3 s
  613. 45: mad f32 $r2 f32 $r2 f32 c0[0x78] f32 $r4 s
  614. 46: mad f32 $o4 f32 $r0 f32 c0[0x80] f32 $r1 s
  615. 47: mad f32 $o5 f32 $r0 f32 c0[0x84] f32 $r3 s
  616. 48: mad f32 $o6 f32 $r0 f32 c0[0x88] f32 $r2 s
  617. preparing 1 blocks for emission
  618. emitting program: size = 392
  619. 0xc0800001 0x00200780 0xc0810005 0x00200780 0xc0820009 0x00200780 0xc083000d 0x00200780 0xe0840201 0x00200780 0xe0850205 0x00204780 0xe0860209 0x00208780 0xe087020d 0x0020c780
  620. 0xe0880401 0x00200780 0xe0890405 0x00204780 0xe08a0409 0x00208780 0xe08b040d 0x0020c780 0xe08c0601 0x00200788 0xe08d0605 0x00204788 0xe08e0609 0x00208788 0xe08f060d 0x0020c788
  621. 0x10000801 0x0423c780 0xc0000801 0x00200780 0x10000a05 0x0423c780 0xe0010a01 0x00200780 0x10000c05 0x0423c780 0xe0010c01 0x00200780 0x90000001 0x40100780 0xc0000805 0x00200780
  622. 0xc0000a09 0x00200780 0xc0000c01 0x00200780 0x10002011 0x2400c788 0x10002215 0x2400c788 0x10002419 0x2400c788 0x1000261d 0x2400c788 0xc0940205 0x00000780 0xe0950405 0x00004780
  623. 0xe0960001 0x00004780 0x10008005 0x00000003 0xb0000209 0x80000780 0xb0000201 0x60004780 0xa0000001 0x44114780 0x10003005 0x2400c780 0xb1000205 0x00040780 0x1000320d 0x2400c780
  624. 0xb100060d 0x00044780 0x10003411 0x2400c780 0xb1000811 0x00048780 0xe09c0405 0x00004780 0xe09d040d 0x0000c780 0xe09e0409 0x00010780 0xe0a00011 0x00004788 0xe0a10015 0x0000c788
  625. 0xe0a20019 0x00008789
  626. SHADER TRANSLATION - success
  627. Uploading code to offset 0007fc00, len 392
  628. migrating 32 KiB to VRAM
  629. MM: new slab, total memory = 128 KiB
  630. 7251 frames in 5.0 seconds = 1450.184 FPS
  631. 5636 frames in 5.0 seconds = 1127.100 FPS
  632. 6509 frames in 5.0 seconds = 1301.800 FPS
  633. 6142 frames in 5.0 seconds = 1228.208 FPS
  634. 7464 frames in 5.0 seconds = 1492.790 FPS
  635. 7404 frames in 5.0 seconds = 1480.691 FPS
  636. 6197 frames in 5.0 seconds = 1239.379 FPS
  637. 7492 frames in 5.0 seconds = 1498.379 FPS
  638. 5955 frames in 5.0 seconds = 1190.938 FPS
  639. 7167 frames in 5.0 seconds = 1433.293 FPS
  640. 7410 frames in 5.0 seconds = 1481.840 FPS
  641. 6387 frames in 5.0 seconds = 1277.237 FPS
  642. ^C
  643. [diego@myhost ~]$
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