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  1. /*
  2. * This devicetree is generated by sopc2dts
  3. * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
  4. * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
  5. */
  6. /dts-v1/;
  7.  
  8. / {
  9. model = "ALTR,DE2_70_SOPC";
  10. compatible = "ALTR,DE2_70_SOPC";
  11. #address-cells = < 1 >;
  12. #size-cells = < 1 >;
  13.  
  14. cpus {
  15. #address-cells = < 1 >;
  16. #size-cells = < 0 >;
  17.  
  18. cpu_m: cpu@0x0 {
  19. device_type = "cpu";
  20. compatible = "ALTR,nios2-11.1";
  21. reg = < 0x00000000 >;
  22. interrupt-controller;
  23. #interrupt-cells = < 1 >;
  24. clock-frequency = < 100000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */
  25. dcache-line-size = < 0 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */
  26. icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */
  27. dcache-size = < 0 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */
  28. icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */
  29. ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/
  30. ALTR,pid-num-bits = < 10 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */
  31. ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */
  32. ALTR,tlb-num-entries = < 128 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */
  33. ALTR,tlb-ptr-sz = < 7 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */
  34. ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/
  35. ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */
  36. ALTR,fast-tlb-miss-addr = < 0xc0000020 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */
  37. ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */
  38. }; //end cpu@0x0 (cpu_m)
  39. }; //end cpus
  40.  
  41. memory@0 {
  42. device_type = "memory";
  43. reg = < 0x08000000 0x00002000
  44. 0x00000000 0x02000000
  45. 0x02000000 0x02000000
  46. 0x07000000 0x00200000 >;
  47. }; //end memory@0
  48.  
  49. sopc@0 {
  50. ranges;
  51. #address-cells = < 1 >;
  52. #size-cells = < 1 >;
  53. device_type = "soc";
  54. compatible = "ALTR,avalon", "simple-bus";
  55. bus-frequency = < 100000000 >;
  56.  
  57. cfi_flash: flash@0x5000000 {
  58. compatible = "ALTR,cfi_flash-11.1", "cfi-flash";
  59. reg = < 0x05000000 0x00800000 >;
  60. bank-width = < 2 >;
  61. device-width = < 1 >;
  62. }; //end flash@0x5000000 (cfi_flash)
  63.  
  64. pio_green_led: gpio@0x9001080 {
  65. compatible = "ALTR,pio-11.1", "ALTR,pio-1.0";
  66. reg = < 0x09001080 0x00000010 >;
  67. width = < 9 >; /* width type NUMBER */
  68. resetvalue = < 0 >; /* resetValue type NUMBER */
  69. }; //end gpio@0x9001080 (pio_green_led)
  70.  
  71. pio_switch: gpio@0x90010c0 {
  72. compatible = "ALTR,pio-11.1", "ALTR,pio-1.0";
  73. reg = < 0x090010C0 0x00000010 >;
  74. width = < 18 >; /* width type NUMBER */
  75. resetvalue = < 0 >; /* resetValue type NUMBER */
  76. }; //end gpio@0x90010c0 (pio_switch)
  77.  
  78. pio_button: gpio@0x9001100 {
  79. compatible = "ALTR,pio-11.1", "ALTR,pio-1.0";
  80. reg = < 0x09001100 0x00000010 >;
  81. interrupt-parent = < &cpu_m >;
  82. interrupts = < 3 >;
  83. width = < 4 >; /* width type NUMBER */
  84. resetvalue = < 0 >; /* resetValue type NUMBER */
  85. }; //end gpio@0x9001100 (pio_button)
  86.  
  87. sysid: sysid@0x9001180 {
  88. compatible = "ALTR,sysid-11.1", "ALTR,sysid-1.0";
  89. reg = < 0x09001180 0x00000008 >;
  90. }; //end sysid@0x9001180 (sysid)
  91.  
  92. timer_cpu_m: timer@0x9001000 {
  93. compatible = "ALTR,timer-11.1", "ALTR,timer-1.0";
  94. reg = < 0x09001000 0x00000020 >;
  95. interrupt-parent = < &cpu_m >;
  96. interrupts = < 0 >;
  97. clock-frequency = < 100000000 >;
  98. }; //end timer@0x9001000 (timer_cpu_m)
  99.  
  100. jtag_uart_cpu_m: serial@0x9001040 {
  101. compatible = "ALTR,juart-11.1", "ALTR,juart-1.0";
  102. reg = < 0x09001040 0x00000008 >;
  103. interrupt-parent = < &cpu_m >;
  104. interrupts = < 2 >;
  105. }; //end serial@0x9001040 (jtag_uart_cpu_m)
  106.  
  107. dm9000: unknown@0x9001140 {
  108. compatible = "unknown,unknown-1.0";
  109. reg = < 0x09001140 0x00000008 >;
  110. interrupt-parent = < &cpu_m >;
  111. interrupts = < 1 >;
  112. }; //end unknown@0x9001140 (dm9000)
  113.  
  114. clock_generator: clock@0x9080000 {
  115. compatible = "ALTR,pll-11.1", "ALTR,pll-1.0";
  116. reg = < 0x09080000 0x00000010 >;
  117. }; //end clock@0x9080000 (clock_generator)
  118. }; //end sopc@0
  119.  
  120. chosen {
  121. bootargs = "debug console=ttyJ0,115200";
  122. }; //end chosen
  123. }; //end /
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