//module testbench();
//
//timeunit 10ns;
//
//timeprecision 1ns;
//
////logic CLK;
////logic RESET;
////logic AVL_READ;
////logic AVL_WRITE;
////logic AVL_CS;
////logic [3:0] AVL_BYTE_EN;
////logic [3:0] AVL_ADDR;
////logic [31:0] AVL_WRITEDATA;
////logic [31:0] AVL_READDATA;
////logic [31:0] EXPORT_DATA;
////
////interface_top interf(.*);
//
//
//logic CLK;
//logic RESET;
//logic AES_START;
//logic AES_DONE;
//logic [127:0] AES_KEY;
//logic [127:0] AES_MSG_ENC;
//logic [127:0] AES_MSG_DEC;
//
//AES aes(.*);
//
//always begin : CLOCK_GENERATION
//    #1 CLK = ~CLK;
//end
//
//initial begin : CLOCK_INIT
//    CLK = 0;
//end
//
//initial begin : TEST_VECTORS
//    RESET = 1'b1;
//
//    #2 RESET = 1'b0;
//
//    AES_KEY = 128'h000102030405060708090a0b0c0d0e0f;
//    AES_MSG_ENC = 128'hdaec3055df058e1c39e814ea76f6747e;
//
//    #2 AES_START = 1'b1;
//    #2 AES_START = 1'b0;
//
//end
//
//endmodule

module testbench();

timeunit 10ns;

timeprecision 1ns;

logic CLK;
logic RESET;
logic AVL_READ;
logic AVL_WRITE;
logic AVL_CS;
logic [3:0] AVL_BYTE_EN;
logic [3:0] AVL_ADDR;
logic [31:0] AVL_WRITEDATA;
logic [31:0] AVL_READDATA;
logic [31:0] EXPORT_DATA;

interface_top interf(.*);


//INTERFACE POV
//Write to registers 0-3, and 4-7 to insert key, and encoded msg
//write to register 14 to set START


//AES POV
logic [127:0] AES_KEY;
logic [127:0] AES_MSG_ENC;
logic [127:0] AES_MSG_DEC;
//logic [127:0] stateOut;

assign AES_KEY = interf.stupid.aes.AES_KEY;
assign AES_MSG_ENC = interf.stupid.aes.AES_MSG_ENC;
assign AES_MSG_DEC = interf.stupid.aes.AES_MSG_DEC;
//assign stateOut = interf.stupid.aes.stateOut;


//ACTUAL TESTBENCH
always begin : CLOCK_GENERATION
    #1 CLK = ~CLK;
end

initial begin : CLOCK_INIT
    CLK = 0;
end

initial begin : TEST_VECTORS
    AVL_CS = 1'b1;
    AVL_READ = 1'b0;
    RESET = 1'b1;
    #2 RESET = 1'b0;

    //WRITES IN KEY
    #2 AVL_BYTE_EN = 4'b1111;
    AVL_ADDR = 4'b0011;
    AVL_WRITEDATA = 32'h00010203;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0010;
    AVL_WRITEDATA = 32'h04050607;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0001;
    AVL_WRITEDATA = 32'h08090a0b;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0000;
    AVL_WRITEDATA = 32'h0c0d0e0f;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    //WRITES IN MSG_ENC
    #2 AVL_ADDR = 4'b0111;
    AVL_WRITEDATA = 32'hdaec3055;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0110;
    AVL_WRITEDATA = 32'hdf058e1c;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0101;
    AVL_WRITEDATA = 32'h39e814ea;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0100;
    AVL_WRITEDATA = 32'h76f6747e;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    //WRITES IN START REG
    #2 AVL_ADDR = 4'b1110;
    AVL_WRITEDATA = 32'h00000001;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b1110;
    AVL_WRITEDATA = 32'h00000000;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    //CONSECUTIVE TEST
     #425
     AVL_CS = 1'b1;
    AVL_READ = 1'b0;
    RESET = 1'b1;
    #2 RESET = 1'b0;

    //WRITES IN KEY
    #2 AVL_BYTE_EN = 4'b1111;
    AVL_ADDR = 4'b0011;
    AVL_WRITEDATA = 32'h3b280014;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0010;
    AVL_WRITEDATA = 32'hbeaac269;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0001;
    AVL_WRITEDATA = 32'hd613a16b;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0000;
    AVL_WRITEDATA = 32'hfdc2be03;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    //WRITES IN MSG_ENC
    #2 AVL_ADDR = 4'b0111;
    AVL_WRITEDATA = 32'h439d6199;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0110;
    AVL_WRITEDATA = 32'h20ce4156;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0101;
    AVL_WRITEDATA = 32'h61019634;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b0100;
    AVL_WRITEDATA = 32'hf59fcf63;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    //WRITES IN START REG
    #2 AVL_ADDR = 4'b1110;
    AVL_WRITEDATA = 32'h00000001;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;

    #2 AVL_ADDR = 4'b1110;
    AVL_WRITEDATA = 32'h00000000;
    AVL_WRITE = 1'b1;
    #2 AVL_WRITE = 1'b0;
end


endmodule