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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity lab3_1 is
- port(
- c0, c1, c2, c3, s1, s2: in std_logic;
- y : out std_logic_vector(0 to 6);
- z : out std_logic_vector(0 to 3)
- );
- end lab3_1;
- architecture struct of lab3_1 is
- component Vhdl3 is
- port(
- c0, c1, c2, c3, s1, s2: in std_logic;
- z : out std_logic_vector(0 to 3)
- );
- end component;
- component Vhdl4 is
- port(
- c0, c1, c2, c3: in std_logic;
- y : out std_logic_vector(0 to 6)
- );
- end component;
- begin
- M: Vhdl3 port map (c0, c1, c2, c3, s1, s2, z);
- H: Vhdl4 port map (c0, c1, c2, c3, y);
- end struct;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity Vhdl3 is
- port(
- c0, c1, c2, c3, s1, s2: in std_logic;
- z : out std_logic_vector(0 to 3)
- );
- end Vhdl3;
- architecture mux of Vhdl3 is
- begin
- z <= c0 & "000" when s1 = '0' and s2 = '0' else
- "0" & c1 & "00"when s1 = '0' and s2 = '1' else
- "00" & c2 & "0" when s1 = '1' and s2 = '0' else
- "000" & c3 when s1 = '1' and s2 = '1';
- end mux;
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity Vhdl4 is
- port(
- c0, c1, c2, c3: in std_logic;
- y : out std_logic_vector(0 to 6)
- );
- end Vhdl4;
- architecture display of Vhdl4 is
- begin
- y <= "0000001" when c0 = '0' and c1 = '0' and c2 = '0' and c3 = '0' else
- "1001111" when c0 = '0' and c1 = '0' and c2 = '0' and c3 = '1' else
- "0010010" when c0 = '0' and c1 = '0' and c2 = '1' and c3 = '0' else
- "0000110"when c0 = '0' and c1 = '0' and c2 = '1' and c3 = '1' else
- "1001100" when c0 = '0' and c1 = '1' and c2 = '0' and c3 = '0' else
- "0100100" when c0 = '0' and c1 = '1' and c2 = '0' and c3 = '1' else
- "0100000" when c0 = '0' and c1 = '1' and c2 = '1' and c3 = '0' else
- "0001111" when c0 = '0' and c1 = '1' and c2 = '1' and c3 = '1' else
- "0000000" when c0 = '1' and c1 = '0' and c2 = '0' and c3 = '0' else
- "0000100" when c0 = '1' and c1 = '0' and c2 = '0' and c3 = '1';
- end display;
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