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emresm

4bitRegist

Mar 13th, 2021
371
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4.  
  5. entity reg4 is
  6.     port (d0, d1, d2, d3, en, clk : in bit;
  7.             q0, q1, q2, q3 : out bit);
  8. end entity reg4;
  9.  
  10.  
  11. architecture behavioral of reg4 is
  12. begin
  13.  
  14.     storage : process is
  15.         variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
  16.         --when process is suspended, process variables are not lost
  17.     begin
  18.         wait until clk;
  19.         if en then
  20.             stored_d0 := d0;
  21.             stored_d1 := d1;
  22.             stored_d2 := d2;
  23.             stored_d3 := d3;
  24.         end if;
  25.         q0 <= stored_d0 after 5ns;
  26.         q1 <= stored_d1 after 5ns;
  27.         q2 <= stored_d2 after 5ns;
  28.         q3 <= stored_d3 after 5ns;
  29.     end process storage;
  30. end behavioral;
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