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Paragon mr resolution

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    15:03:30 12/18/2019
  6. -- Design Name:
  7. -- Module Name:    zamekv2 - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity zamekv2 is
  33.     Port ( Dio : in  STD_LOGIC_VECTOR (7 downto 0);
  34.            reset : in  STD_LOGIC;
  35.            E0 : in  STD_LOGIC;
  36.            F0 : in  STD_LOGIC;
  37.            dio_rdy : in  STD_LOGIC;
  38.            y : out  STD_LOGIC;
  39.            on_unlock : out  STD_LOGIC;
  40.            st : out  STD_LOGIC_VECTOR (3 downto 0));
  41. end zamekv2;
  42.  
  43. architecture Behavioral of zamekv2 is
  44.  
  45. type state_type is (S0, S1, S2, S3, S4);
  46. signal state, next_state : state_type;
  47.  
  48. begin
  49. SYNC_PROC : process (dio_rdy)
  50. begin
  51.     if rising_edge(dio_rdy) then  
  52.         if (reset = '1') then  
  53.             state <= S0;  
  54.         elsif dio_rdy = '1' and F0 = '1' then
  55.             state <= next_state;  
  56.         end if;
  57.     end if;
  58. end process;
  59.  
  60. OUTPUT_DECODE : process (state)
  61. begin  
  62.     case (state) is  
  63.         when S4 =>    
  64.             y <= '1';
  65.         when others =>
  66.             y <= '0';
  67.     end case;
  68. end process;
  69.  
  70. ST_DECODE : process (state)
  71. begin  
  72.     case (state) is  
  73.         when S0 =>    
  74.             st <= "0000" ;
  75.         when S1 =>  
  76.             st <= "0001" ;
  77.         when S2 =>  
  78.             st <= "0010" ;
  79.         when S3 =>  
  80.             st <= "0011" ;
  81.         when S4 =>  
  82.             st <= "0100" ;
  83.     end case;
  84. end process;
  85.  
  86. ON_UNLOCK_DECODE : process (state, F0, dio_rdy)
  87. begin  
  88.     IF (state = S4 AND F0 = '1' AND dio_rdy = '1') THEN  
  89.         on_unlock <= '1';
  90.     else
  91.         on_unlock <= '0';
  92.     end IF;
  93. end process;
  94.  
  95. NEXT_STATE_DECODE : process (state, dio)
  96. begin  
  97.     next_state <= S0;  
  98.     case (state) is  
  99.         when S0 =>    
  100.             if (dio = X"1D") then    
  101.                 next_state <= S1;
  102.             end if;    
  103.         when S1 =>    
  104.             if (dio = X"42") then    
  105.                 next_state <= S2;  
  106.             elsif   (dio = X"1D") then
  107.                 next_state <= S1;
  108.             end if;  
  109.         when S2 =>    
  110.             if (dio = X"2B") then    
  111.                 next_state <= S3;  
  112.             elsif (dio = X"1D") then    
  113.                 next_state <= S1;
  114.             end if;
  115.         when S3 =>    
  116.             if (dio = X"1D") then    
  117.                 next_state <= S4;  
  118.             end if;    
  119.         when S4 =>    
  120.             if (dio = X"42") then    
  121.                 next_state <= S2;  
  122.             elsif   (dio = X"1D") then
  123.                 next_state <= S1;
  124.             end if;
  125.     end case;
  126. end process;
  127. end architecture;
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