cursofpgavhdl

decodificador_BCD

Jul 30th, 2020 (edited)
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  1. -- PROJETO: sete seg dataflow sem vetor
  2. -- ENTRADA A, B, C, D (tipo bit)
  3. -- SAIDA: SA, SB, SC, SD, SD, SF, SG (tipo bit)
  4. -- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL TERFERNANDES
  5. -- DATA: 22/06/2020
  6. ----------------------------------------------------------
  7. entity decodificador_BCD is
  8.     Port ( A, B, C, D : in bit;    
  9.            SA, SB, SC, SD, SE, SF, SG : out bit);
  10. end decodificador_BCD;
  11. ----------------------------------------------------------
  12. architecture arquitetura of decodificador_BCD is
  13. begin
  14.     SA <= not (A or C or (B xnor D));
  15.     SB <= not ((not B) or (C xnor D));
  16.     SC <= not (B or (not C) or D);
  17.     SD <= not (A or ((not B) and (not D)) or ((not B) and C) or
  18.                (C and (not D)) or (B and (not C) and D));
  19.     SE <= not (((not B) and (not D)) or (C and (not D)));
  20.     SF <= not (A or ((not C) and (not D)) or (B and (not C)) or (B and (not D)));
  21.     SG <= not (A or (B xor C) or (C and (not D)));
  22. end arquitetura;
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