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-- Company:
-- Engineer:
--
-- Create Date:    15:32:02 11/10/2010
-- Design Name:
-- Module Name:    new_mod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity new_mod is
    Port ( DI : in  STD_LOGIC_VECTOR (7 downto 0);
           DO : out  STD_LOGIC_VECTOR (7 downto 0);
           DIRdy : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
			  Clk : in  STD_LOGIC;
			  TxBusy : in  STD_LOGIC;
			  DORdy : out  STD_LOGIC;
			  Busy : out  STD_LOGIC);
end new_mod;

architecture RTL of new_mod is

type state_type is (sReset, sReady, sWaitH, sSendH, sWaitL, sSendL);

signal State, NextState: state_type;
signal regDI: STD_LOGIC_VECTOR (7 downto 0);
signal HalfByte : STD_LOGIC_VECTOR (3 downto 0);


begin

regDI <= DI when rising_edge( Clk ) and State = sReady ;
HalfByte <= regDI( 7 downto 4 ) when State = sSendH or State = sWaitL
		else regDI( 3 downto 0 );

process ( Clk, Reset )
begin
	if Reset = '1' then
		State <= sReset;
	elsif rising_edge( Clk ) then
		State <= NextState;
	end if;
end process;


process (State, DIRdy, TxBusy)
begin
NextState <= State;
case State is
	when sReset =>
		NextState <=sReady;

	when sReady =>
		if DIRdy = '1' then
			NextState <= sWaitH;
		end if;

	when sWaitH =>
		if TxBusy = '0' then
			NextState <= sSendH;
		end if;

	when sSendH =>
		NextState <= sWaitL;

	when sWaitL =>
		if TxBusy = '0' then
			NextState <= sSendL;
		end if;

	when sSendL =>
		NextState <= sReady;

	end case;
end process;

with HalfByte select
	DO <= X"30" when "0000",
			X"31" when "0001",
			X"32" when "0010",
			X"33" when "0011",
			X"34" when "0100",
			X"35" when "0101",
			X"36" when "0110",
			X"37" when "0111",
			X"38" when "1000",
			X"39" when "1001",
			X"41" when "1010",
			X"42" when "1011",
			X"43" when "1100",
			X"44" when "1101",
			X"45" when "1110",
			X"46" when others;

DORdy <= '1' when State = sSendH or State = sSendL
	else '0';

Busy <= '1' when State /= sReady
	else '0';


end RTL;