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-- Company:
-- Engineer:
--
-- Create Date: 05/15/2018 07:21:22 PM
-- Design Name:
-- Module Name: DCDI - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DCDI is
    Port ( intrare : in STD_LOGIC_VECTOR (31 downto 0);
           RegWr : out STD_LOGIC;
           AdrD : out STD_LOGIC;
           MxD : out STD_LOGIC_VECTOR(1 downto 0);
           SSalt : out STD_LOGIC_VECTOR(1 downto 0);
           CSalt : out STD_LOGIC;
           MemWr : out STD_LOGIC;
           OpUAL : out STD_LOGIC_VECTOR(3 downto 0);
           MxA : out STD_LOGIC;
           MxB : out STD_LOGIC;
           AdrSA : out STD_LOGIC;
           AdrSB : out STD_LOGIC;
           SelC : out STD_LOGIC);
end DCDI;

architecture Behavioral of DCDI is
signal codop: std_logic_vector(7 downto 0);
begin
codop<=intrare(31 downto 24);

process(codop)
begin
case codop is
  when B"0100_0000" => OpUAL<="0000"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_0010" => OpUAL<="0010"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_0101" => OpUAL<="0101"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1000" => OpUAL<="1000"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1001" => OpUAL<="1001"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1010" => OpUAL<="1010"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1011" => OpUAL<="1011"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0010_0010" => OpUAL<="0010"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='1';
  when B"0010_0101" => OpUAL<="0101"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='1';
  when B"0010_1000" => OpUAL<="1000"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='0';
  when B"0010_1001" => OpUAL<="1001"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='0';
  when B"0010_1010" => OpUAL<="1010"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='0';
  when B"0100_0010" => OpUAL<="0010"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='0';
  when B"0100_0101" => OpUAL<="0101"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='1'; SelC<='0';
  when B"0000_1100" => OpUAL<="1100"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1101" => OpUAL<="1101"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';
  when B"0000_1110" => OpUAL<="1110"; RegWr<='0'; MxD<="00"; SSalt<="00"; CSalt<='0'; MemWr<='0'; MxA<='0'; MxB<='0'; SelC<='0';

  end case;
end process;

end Behavioral;