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- OBJCFLAGS = -lobjc -framework Foundation
- CFLAGS = -fblocks
- CXXFLAGS =
- DEPS = mylog.h
- EXES = test_objc test_c test_cpp \
- mem_leak_objc mem_leak_objc_gc mem_leak_c mem_leak_cpp
- .PHONY: all clean
- .SUFFIXES: .c .cpp .m .o
- # These make an executable from file with the same name but with the given
- # extension. These are already defined by make, but I'm changing the order of
- # args a little:
- # Although .m: is defined by make, it doesn't take $(OBJCFLAGS) into account
- # for whatever reason, so the Cocoa and Objective-C libs don't get linked in.
- .m: $(DEPS)
- gcc -o $@ $< $(OBJCFLAGS)
- .c: $(DEPS)
- gcc -o $@ $< $(CFLAGS)
- .cpp: $(DEPS)
- g++ -o $@ $< $(CXXFLAGS)
- # We can also use lines like .m.o: to handle making .o files from .m files.
- all: $(EXES)
- $(EXES): $(DEPS)
- # TODO: How do we make it so that each executable depends on a similarly-named
- # source file? Right now, if there's a name in $(EXES) that doesn't exist in
- # source form, make treats the target as already done.
- clean:
- -rm -f $(EXES)
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