typedef struct {
    uint16_t config;
    spi_transaction_t *trans;
    gpio_config_t *gpio_conf;
    spi_device_handle_t *spidev;
    spi_device_interface_config_t *ifcfg;
    spi_bus_config_t *buscfg;
} ads1118_handle_t;

void ads1118_setup(spi_device_handle_t *spidev, spi_bus_config_t *buscfg, spi_device_interface_config_t *ifcfg, ads1118_handle_t *ads_dev){

    //ads1118_handle_t ads_dev;

    ads_dev->spidev = spidev;
    ads_dev->ifcfg = ifcfg;
    ads_dev->buscfg = buscfg;
    ads_dev->trans->length = 16; // In bits. Use 16 for
    ads_dev->trans->flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA;
    ads_dev->trans->user = (void*)1;
    ads_dev->trans->cmd = 0; // 16 bit Command data, length < command_bits in ifcfg
    ads_dev->trans->addr = 0; // 64 bit Address data, len < address_bits in ifcfg
    ads_dev->trans->rxlength = 0; // Defaults to value of length
    ads_dev->trans->user=(void*)1; // Pointer to some user-defined transaction ID
    //ads1118_spi_trans.tx_data[0] = 0xFF; // Only used if SPI_TRANS_USE_TXDATA is set in .flags, otherwise uses tx_buffer
    //ads1118_spi_trans.tx_data[1] = 0x00; // Only used if SPI_TRANS_USE_TXDATA is set in .flags, otherwise uses tx_buffer
    //ads1118_spi_trans.rx_data  = ;// Presumably you'd never set this here as it's for receiving. Used if appropriate flag is set.
    // Also consider *tx_buffer and *rx_buffer which you'll probably not set here

    ads_dev->gpio_conf->intr_type = GPIO_PIN_INTR_DISABLE;
    ads_dev->gpio_conf->mode = GPIO_MODE_OUTPUT;
    ads_dev->gpio_conf->pin_bit_mask = 1ULL<<ifcfg->spics_io_num; // FIXME: Generalise
    ads_dev->gpio_conf->pull_down_en = 0;
    ads_dev->gpio_conf->pull_up_en = 0;

    ads_dev->config = 0x058B; // Default settings per datasheet
    ads_dev->trans->tx_data[0] = ads_dev->config >> 8;
    ads_dev->trans->tx_data[1] = ads_dev->config & 0xFF;

    //return ads_dev;

}

void ads1118_read(ads1118_handle_t *ads_dev){

    esp_err_t ret;
    ads_dev->trans->tx_data[0] |= (1<<7); // Sets bit 15 in the 16 bit value in tx_data, single shot
    ret = spi_device_transmit(ads_dev->spidev, ads_dev->trans); // FIXME: Go async
    assert( ret == ESP_OK );
    ret = spi_bus_remove_device(ads_dev.spidev);
    assert( ret == ESP_OK );
    ret = gpio_config(&ads_dev.gpio_conf);
    assert( ret == ESP_OK );
    gpio_set_level(ads_dev.ifcfg.spics_io_num,0); // Assert CS. Don't deassert, because readding the SPI device later will do that
    assert( ret == ESP_OK );
    while(gpio_get_level(ads_dev.buscfg.sclk_io_num) != 0){
        // FIXME: Essential: Some sort of way out if it never happens
        vTaskDelay(1/portTICK_PERIOD_MS);
    }
    ret=spi_bus_add_device(HSPI_HOST, &ads_dev.ifcfg, &ads_dev.spidev);
    assert( ret == ESP_OK );
    int16_t y = ads_dev.trans.rx_data[1] + ads_dev.trans.rx_data[0]*256;
    printf("Read: %d\r\n", y);

}

void app_main()
{

    // SPI
    // miso, mosi, clock, cs = 16, 17, 18, 19

    spi_device_handle_t spi;
    esp_err_t ret;
    spi_bus_config_t buscfg={
        .miso_io_num=16,
        .mosi_io_num=17,
        .sclk_io_num=18,
        //.flags // Abilities of bus to be checked by the driver. Or-ed value of SPICOMMON_BUSFLAG_* flags.
        //.max_transfer_sz, // In bytes, default 4096 if 0.
        //.quadwp_io_num=-1, // Write Protect signal for 4 bit modes, or -1
        //.quadhd_io_num=-1, // HoID signal for 4 bit modes, or -1
        //.max_transfer_sz=PARALLEL_LINES*320*2+8
        //.intr_flags // Interrupt flag for the bus to set the priority, and IRAM attribute, see docs
    };

    spi_device_interface_config_t ifcfg={
        .clock_speed_hz=1000000,           //Clock out at 1MHz
        .mode=1,                                //SPI mode 1 for ADS1118; clock idles low and goes low mid-bit
        .spics_io_num=19,               //CS pin
        .queue_size=1,                          // max number of queue_trans() without get_trans_result()
        //.pre_cb=spi_dummy_callback,  //Specify pre-transfer callback. Callback should be in RAM. (Cache miss?)
        //.post_cb // Post-transfer callback. Again, IRAM.
        //.command_bits=0,
        //.address_bits=0,
        //.dummy_bits=0,
        .cs_ena_pretrans=1, // CS becomes active 0-16 bits before transmission. ADS1118 seems to need 1 clock.
        //.cs_ena_posttrans=0, // CS stays active 0-16 bits after transmission
        //.duty_cycle_pos=0, // Clock duty cycle in 1/256.. 128 = 0 = default.
        //.input_delay_ns // Offset clock skew. Effectively sets data valid time on stuff we receive.
    };

    ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); // Last arg is dma channel. NB, ISR runs on core that called this.
    assert( ret == ESP_OK );
    ret=spi_bus_add_device(HSPI_HOST, &ifcfg, &spi);
    assert( ret == ESP_OK );
    ads1118_handle_t ads_dev;
    ads1118_setup(&spi, &buscfg, &ifcfg, &ads_dev);

    while(1) {

        ads1118_read(&ads_dev);
        vTaskDelay(100/portTICK_PERIOD_MS);

    }
}