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  1. library ieee ;
  2.  
  3. use ieee.std_logic_1164.all;
  4.  
  5. use ieee.std_logic_unsigned.all;
  6.  
  7. entity vhdl_lab8 is
  8.  
  9. port( writedata: in std_logic_vector(31 downto 0);
  10.  
  11.       clk_clk, reset_reset_n:   in std_logic;
  12.  
  13.       wr, cs : in std_logic;
  14.        
  15.       ERRHEX : out std_logic_vector(0 to 6);
  16.         ERRLED: out std_logic;
  17.        
  18.       HEX : out std_logic_vector(0 to 6);
  19.  
  20.       LED: out std_logic
  21. );
  22. end vhdl_lab8;
  23.  
  24.  
  25.  
  26. architecture rtl of vhdl_lab8 is
  27.  
  28. signal reg: std_logic_vector(5 downto 0);
  29.  
  30. signal licznik: std_logic_vector(25 downto 0);      
  31.  
  32. begin
  33.  
  34. process(clk_clk)
  35.  
  36. begin
  37.  
  38.    if (clk_clk'event and clk_clk='1') then
  39.  
  40.       if(wr='1' and cs='1') then
  41.  
  42.         reg <=writedata(5 downto 0);
  43.         end if;
  44.  
  45.     end if;
  46.  
  47. end process;
  48.  
  49.  
  50.  
  51. process(clk_clk)
  52.  
  53. begin
  54.     if(reg="000010") then
  55.         LED <= '1';
  56.         HEX <= "0100100";
  57.         ERRLED <= '0';
  58.         ERRHEX <= "1111111";
  59.     elsif (reg="000000") then
  60.         LED <= '0';
  61.         HEX <= "1111111";
  62.         ERRLED <= '0';
  63.         ERRHEX <= "1111111";
  64.     elsif (reg/="000000") and (reg/="000001") and (reg/="000010") and (reg/="000100") and (reg/="001000") and (reg/="010000") and (reg/="100000") then
  65.         LED <= '0';
  66.         HEX <= "1111111";
  67.         ERRLED <= '1';
  68.         ERRHEX <= "0000110";
  69.     end if;
  70. --   if (clk_clk'event and clk_clk='1') then
  71. --
  72. --      licznik <= licznik +1;
  73. --
  74. --    -- 1 okres=1.34s
  75. --
  76. --      if (reg="0000") then vhdl_lab8_out <= '0';
  77. --
  78. --      elsif (reg="1111") then vhdl_lab8_out <= '1';
  79. --
  80. --      elsif (licznik(25 downto 22) = "0000") then vhdl_lab8_out <= '1';
  81. --
  82. --      elsif (licznik(25 downto 22) = reg) then  vhdl_lab8_out <= '0';
  83. --
  84. --      end if;
  85. --
  86. --    end if;
  87.  
  88. end process;
  89.  
  90. end rtl;
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