library ieee ;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity vhdl_lab8 is

port( writedata: in std_logic_vector(31 downto 0);

      clk_clk, reset_reset_n:   in std_logic;

      wr, cs : in std_logic;

      ERRHEX : out std_logic_vector(0 to 6);
		ERRLED: out std_logic;

      HEX : out std_logic_vector(0 to 6);

      LED: out std_logic
);
end vhdl_lab8;



architecture rtl of vhdl_lab8 is

signal reg: std_logic_vector(5 downto 0);

signal licznik: std_logic_vector(25 downto 0);

begin

process(clk_clk)

begin

   if (clk_clk'event and clk_clk='1') then

      if(wr='1' and cs='1') then

        reg <=writedata(5 downto 0);
        end if;

    end if;

end process;



process(clk_clk)

begin
	if(reg="000010") then
		LED <= '1';
		HEX <= "0100100";
		ERRLED <= '0';
		ERRHEX <= "1111111";
	elsif (reg="000000") then
		LED <= '0';
		HEX <= "1111111";
		ERRLED <= '0';
		ERRHEX <= "1111111";
	elsif (reg/="000000") and (reg/="000001") and (reg/="000010") and (reg/="000100") and (reg/="001000") and (reg/="010000") and (reg/="100000") then
		LED <= '0';
		HEX <= "1111111";
		ERRLED <= '1';
		ERRHEX <= "0000110";
	end if;
--   if (clk_clk'event and clk_clk='1') then
--
--      licznik <= licznik +1;
--
--    -- 1 okres=1.34s
--
--      if (reg="0000") then vhdl_lab8_out <= '0';
--
--      elsif (reg="1111") then vhdl_lab8_out <= '1';
--
--      elsif (licznik(25 downto 22) = "0000") then vhdl_lab8_out <= '1';
--
--      elsif (licznik(25 downto 22) = reg) then  vhdl_lab8_out <= '0';
--
--      end if;
--
--    end if;

end process;

end rtl;