Advertisement
Guest User

Untitled

a guest
Jun 20th, 2018
56
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 3.15 KB | None | 0 0
  1. us.v:
  2.  
  3. `timescale 1ns / 1ps
  4. //////////////////////////////////////////////////////////////////////////////////
  5. // Company:
  6. // Engineer:
  7. //
  8. // Create Date: 02:32:52 06/19/2018
  9. // Design Name:
  10. // Module Name: us
  11. // Project Name:
  12. // Target Devices:
  13. // Tool versions:
  14. // Description:
  15. //
  16. // Dependencies:
  17. //
  18. // Revision:
  19. // Revision 0.01 - File Created
  20. // Additional Comments:
  21. //
  22. //////////////////////////////////////////////////////////////////////////////////
  23. module us(
  24.  
  25. input X1,
  26.  
  27. input X2,
  28.  
  29. input RST,
  30.  
  31. input CLK,
  32.  
  33. output reg Z1,
  34.  
  35. output reg Z2,
  36. output reg Z3,
  37.  
  38. output reg M,
  39.  
  40. output [2:0] _stan,
  41.  
  42. output [7:0] _tim,
  43. output [7:0] _tim2
  44.  
  45. );
  46.  
  47. reg [2:0] stan;
  48.  
  49. reg [7:0] tim;
  50. reg [7:0] tim2;
  51. reg [31:0] cnt1;
  52. reg CLK2;
  53.  
  54.  
  55.  
  56. always@(posedge CLK)
  57. if(cnt1 < 2500000) cnt1<=cnt1+1;
  58. else begin cnt1<=0; CLK2<=~CLK2; end
  59. always@(posedge CLK2)
  60.  
  61. begin
  62.  
  63. if(~RST) begin tim=30; stan<=1; Z1<=0; Z2<=0; Z3<=0; M<=0; end
  64.  
  65. else
  66.  
  67. begin
  68.  
  69. case(stan)
  70.  
  71. 3'd1: begin Z1<=1; Z2<=0; Z3<=0; M<=0;
  72.  
  73. if(!tim) begin tim=10; stan<=2; end
  74. else
  75. if(X2) begin tim=10; tim2=100; stan<=3; end
  76.  
  77. end
  78.  
  79. 3'd2: begin Z1<=0; Z2<=1; Z3<=0; M<=0;
  80.  
  81. if(!tim) begin tim=30; stan<=1; end
  82.  
  83. else
  84.  
  85. if(X2) begin tim=10; tim2=100; stan<=3; end
  86.  
  87. end
  88.  
  89. 3'd3: begin Z1<=0; Z2<=0; Z3<=0; M<=1;
  90.  
  91. if(!tim) begin tim=10; stan<=4; end
  92. else
  93. if (!tim2) begin tim=20; stan<=5; end
  94.  
  95. end
  96.  
  97. 3'd4:begin Z1<=0; Z2<=0; Z3<=0; M<=0;
  98.  
  99. if(!tim) begin tim=10; stan<=3; end
  100.  
  101. else
  102.  
  103. if(!tim2) begin tim=20; stan<=5; end
  104.  
  105. end
  106.  
  107. 3'd5: begin Z1<=0; Z2<=0; Z3<=1; M<=0;
  108.  
  109. if(!tim&X1) begin tim=10; stan<=6; end
  110. else
  111. if(!X1) begin tim=30; stan<=1; end
  112.  
  113. end
  114.  
  115. 3'd6: begin Z1<=0; Z2<=0; Z3<=0; M<=0;
  116.  
  117. if(!tim) begin tim=20; stan<=5; end
  118.  
  119. end
  120.  
  121. endcase
  122.  
  123.  
  124.  
  125. if(tim) tim=tim-1;
  126.  
  127. if(tim2) tim2=tim2-1;
  128.  
  129. end
  130. end
  131.  
  132.  
  133. assign _stan=stan;
  134.  
  135. assign _tim=tim;
  136. assign _tim2=tim2;
  137.  
  138.  
  139.  
  140. endmodule
  141.  
  142.  
  143. plytka:
  144. NET "X1" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP ;
  145. NET "X2" LOC = "U10" | IOSTANDARD = LVTTL | PULLUP ;
  146. NET "RST" LOC = "T9" | IOSTANDARD = LVTTL | PULLUP ;
  147. NET "CLK" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
  148.  
  149. NET "Z1" LOC = "R20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
  150. NET "Z2" LOC = "T19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
  151. NET "Z3" LOC = "U20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
  152. NET "M" LOC = "U19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement