Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- `timescale 1ns / 1ps
- // in the DECODER AND OPERAND FETCH phase
- // extends the IMMEDIATE from 15 bit to 32 bit
- // depending on CS bit, extends the sign bit (not sure which, COME BACK AND FIND OUT!!)
- module Constant_unit(
- input [14:0] IM,
- input CS,
- output reg [31:0] CONST_DATA
- );
- always@(*) begin
- CONST_DATA = IM;
- CONST_DATA[31] = (CS)? IM[14]: 0 ; // in tables, CS = 1 for sign extended IM
- end
- endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement